Merge remote-tracking branch 'upstream/master' into galp5

Change-Id: I3b61b0368544499706b8416d093e1ceedd1143c6
This commit is contained in:
Jeremy Soller
2020-11-25 14:37:36 -07:00
116 changed files with 793 additions and 788 deletions

2
3rdparty/vboot vendored

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@@ -288,6 +288,13 @@ M: Nico Huber <nico.h@gmx.de>
S: Supported S: Supported
F: src/mainboard/kontron/bsl6/ F: src/mainboard/kontron/bsl6/
KONTRON MAL10 MAINBOARD
M: Maxim Polyakov <max.senia.poliak@gmail.com>
M: Nico Huber <nico.h@gmx.de>
M: Felix Singer <felixsinger@posteo.net>
S: Supported
F: src/mainboard/kontron/mal10/
LENOVO MAINBOARDS LENOVO MAINBOARDS

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@@ -463,6 +463,12 @@ static int get_socket_type(void)
return 0x02; /* Unknown */ return 0x02; /* Unknown */
} }
unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo)
{
return meminfo->ecc_capable ?
MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE;
}
unsigned int __weak smbios_processor_external_clock(void) unsigned int __weak smbios_processor_external_clock(void)
{ {
return 0; /* Unknown */ return 0; /* Unknown */
@@ -1035,8 +1041,7 @@ static int smbios_write_type16(unsigned long *current, int *handle)
t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
t->use = MEMORY_ARRAY_USE_SYSTEM; t->use = MEMORY_ARRAY_USE_SYSTEM;
t->memory_error_correction = meminfo->ecc_capable ? t->memory_error_correction = smbios_memory_error_correction_type(meminfo);
MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE;
/* no error information handle available */ /* no error information handle available */
t->memory_error_information_handle = 0xFFFE; t->memory_error_information_handle = 0xFFFE;

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@@ -491,18 +491,6 @@ config MMCONF_SUPPORT
bool bool
default !NO_MMCONF_SUPPORT default !NO_MMCONF_SUPPORT
config HYPERTRANSPORT_PLUGIN_SUPPORT
bool
default n
config HT_CHAIN_UNITID_BASE
int
default 0
config HT_CHAIN_END_UNITID_BASE
int
default 0
config PCIX_PLUGIN_SUPPORT config PCIX_PLUGIN_SUPPORT
bool bool
default y default y

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@@ -35,7 +35,6 @@ postcar-y += pci_ops.c
ramstage-y += pci_ops.c ramstage-y += pci_ops.c
smm-y += pci_ops.c smm-y += pci_ops.c
ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c
ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c
ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c

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@@ -1,499 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <device/device.h>
#include <device/path.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <device/hypertransport.h>
struct ht_link {
struct device *dev;
unsigned int pos;
unsigned char ctrl_off, config_off, freq_off, freq_cap_off;
};
static struct device *ht_scan_get_devs(struct device **old_devices)
{
struct device *first, *last;
first = *old_devices;
last = first;
/*
* Extract the chain of devices to (first through last) for the next
* hypertransport device.
*/
while (last && last->sibling &&
(last->sibling->path.type == DEVICE_PATH_PCI) &&
(last->sibling->path.pci.devfn > last->path.pci.devfn))
{
last = last->sibling;
}
if (first) {
struct device *child;
/* Unlink the chain from the list of old devices. */
*old_devices = last->sibling;
last->sibling = 0;
/* Now add the device to the list of devices on the bus. */
/* Find the last child of our parent. */
for (child = first->bus->children; child && child->sibling;)
child = child->sibling;
/* Place the chain on the list of children of their parent. */
if (child)
child->sibling = first;
else
first->bus->children = first;
}
return first;
}
static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned int pos)
{
struct ht_link cur[1];
int linkb_to_host;
/* Set the hypertransport link width and frequency. */
/*
* See which side of the device our previous write to set the unitid
* came from.
*/
cur->dev = dev;
cur->pos = pos;
linkb_to_host =
(pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
if (!linkb_to_host) {
cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
} else {
cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
}
/*
* Remember the current link as the previous link, but look at the
* other offsets.
*/
prev->dev = cur->dev;
prev->pos = cur->pos;
if (cur->ctrl_off == PCI_HT_CAP_SLAVE_CTRL0) {
prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
} else {
prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
prev->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
prev->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
}
return 0;
}
static unsigned int ht_lookup_slave_capability(struct device *dev)
{
unsigned int pos;
pos = 0;
do {
pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos);
if (pos) {
u16 flags;
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
printk(BIOS_SPEW, "flags: 0x%04x\n", flags);
if ((flags >> 13) == 0) {
/* Entry is a slave secondary, success... */
break;
}
}
} while (pos);
return pos;
}
static void ht_collapse_early_enumeration(struct bus *bus,
unsigned int offset_unitid)
{
unsigned int devfn;
struct ht_link prev;
u16 ctrl;
/* Initialize the hypertransport enumeration state. */
prev.dev = bus->dev;
prev.pos = bus->cap;
prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
prev.config_off = PCI_HT_CAP_HOST_WIDTH;
prev.freq_off = PCI_HT_CAP_HOST_FREQ;
prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
/* Wait until the link initialization is complete. */
do {
ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
/* Is this the end of the hypertransport chain? */
if (ctrl & (1 << 6))
return;
/* Has the link failed? */
if (ctrl & (1 << 4)) {
/*
* Either the link has failed, or we have a CRC error.
* Sometimes this can happen due to link retrain, so
* lets knock it down and see if its transient.
*/
ctrl |= ((1 << 4) | (1 << 8)); /* Link fail + CRC */
pci_write_config16(prev.dev, prev.pos + prev.ctrl_off,
ctrl);
ctrl = pci_read_config16(prev.dev,
prev.pos + prev.ctrl_off);
if (ctrl & ((1 << 4) | (1 << 8))) {
printk(BIOS_ALERT, "Detected error on "
"Hypertransport link\n");
return;
}
}
} while ((ctrl & (1 << 5)) == 0);
/* Actually, only for one HT device HT chain, and unitid is 0. */
#if !CONFIG_HT_CHAIN_UNITID_BASE
if (offset_unitid)
return;
#endif
/* Check if is already collapsed. */
if ((!offset_unitid) || (offset_unitid
&& (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0)
&& (CONFIG_HT_CHAIN_END_UNITID_BASE
< CONFIG_HT_CHAIN_UNITID_BASE))))) {
struct device dummy;
u32 id;
dummy.bus = bus;
dummy.path.type = DEVICE_PATH_PCI;
dummy.path.pci.devfn = PCI_DEVFN(0, 0);
id = pci_read_config32(&dummy, PCI_VENDOR_ID);
if (!((id == 0xffffffff) || (id == 0x00000000)
|| (id == 0x0000ffff) || (id == 0xffff0000))) {
return;
}
}
/* Spin through the devices and collapse any early HT enumeration. */
for (devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) {
struct device dummy;
u32 id;
unsigned int pos, flags;
dummy.bus = bus;
dummy.path.type = DEVICE_PATH_PCI;
dummy.path.pci.devfn = devfn;
id = pci_read_config32(&dummy, PCI_VENDOR_ID);
if ((id == 0xffffffff) || (id == 0x00000000)
|| (id == 0x0000ffff) || (id == 0xffff0000)) {
continue;
}
dummy.vendor = id & 0xffff;
dummy.device = (id >> 16) & 0xffff;
dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
pos = ht_lookup_slave_capability(&dummy);
if (!pos)
continue;
/* Clear the unitid. */
flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n",
dev_path(&dummy), dummy.vendor, dummy.device);
}
}
static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn,
unsigned int max_devfn,
unsigned int *ht_unitid_base,
unsigned int offset_unitid)
{
/*
* Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this
* function, because of end_of_chain check. Also, we need it to
* optimize link.
*/
unsigned int next_unitid, last_unitid, min_unitid, max_unitid;
struct device *old_devices, *dev, *func, *last_func = NULL;
struct ht_link prev;
int ht_dev_num = 0;
printk(BIOS_SPEW, "%s for bus %02x\n", __func__, bus->secondary);
min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
/*
* Let's record the device of last HT device, so we can set the unitid
* to CONFIG_HT_CHAIN_END_UNITID_BASE.
*/
unsigned int real_last_unitid = 0, end_used = 0;
u8 real_last_pos = 0;
struct device *real_last_dev = NULL;
#endif
/* Restore the hypertransport chain to it's uninitialized state. */
ht_collapse_early_enumeration(bus, offset_unitid);
/* See which static device nodes I have. */
old_devices = bus->children;
bus->children = 0;
/* Initialize the hypertransport enumeration state. */
prev.dev = bus->dev;
prev.pos = bus->cap;
prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
prev.config_off = PCI_HT_CAP_HOST_WIDTH;
prev.freq_off = PCI_HT_CAP_HOST_FREQ;
prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
/* If present, assign unitid to a hypertransport chain. */
max_unitid = next_unitid = min_unitid;
do {
u8 pos;
u16 flags, ctrl;
unsigned int count, static_count;
last_unitid = next_unitid;
/* Wait until the link initialization is complete. */
do {
ctrl = pci_read_config16(prev.dev,
prev.pos + prev.ctrl_off);
/* End of chain? */
if (ctrl & (1 << 6))
goto end_of_chain;
if (ctrl & ((1 << 4) | (1 << 8))) {
/*
* Either the link has failed, or we have a CRC
* error. Sometimes this can happen due to link
* retrain, so lets knock it down and see if
* it's transient.
*/
ctrl |= ((1 << 4) | (1 <<8)); // Link fail + CRC
pci_write_config16(prev.dev,
prev.pos + prev.ctrl_off, ctrl);
ctrl = pci_read_config16(prev.dev,
prev.pos + prev.ctrl_off);
if (ctrl & ((1 << 4) | (1 << 8))) {
printk(BIOS_ALERT, "Detected error on "
"hypertransport link\n");
goto end_of_chain;
}
}
} while ((ctrl & (1 << 5)) == 0);
/* Get and setup the device_structure. */
dev = ht_scan_get_devs(&old_devices);
/* See if a device is present and setup the device structure. */
dev = pci_probe_dev(dev, bus, 0);
if (!dev || !dev->enabled)
break;
/* Find the hypertransport link capability. */
pos = ht_lookup_slave_capability(dev);
if (pos == 0) {
printk(BIOS_ERR, "%s Hypertransport link capability "
"not found", dev_path(dev));
break;
}
/* Update the unitid of the current device. */
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
/*
* If the device has a unitid set and is at devfn 0 we are
* done. This can happen with shadow hypertransport devices,
* or if we have reached the bottom of a HT device chain.
*/
if (flags & 0x1f)
break;
flags &= ~0x1f; /* Mask out base Unit ID. */
count = (flags >> 5) & 0x1f; /* Het unit count. */
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if (offset_unitid) {
/* max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7. */
if (next_unitid > (max_devfn >> 3)) {
if (!end_used) {
next_unitid =
CONFIG_HT_CHAIN_END_UNITID_BASE;
end_used = 1;
} else {
goto end_of_chain;
}
}
}
#endif
flags |= next_unitid & 0x1f;
pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
/* Update the unitid in the device structure. */
static_count = 1;
for (func = dev; func; func = func->sibling) {
func->path.pci.devfn += (next_unitid << 3);
static_count = (func->path.pci.devfn >> 3)
- (dev->path.pci.devfn >> 3) + 1;
last_func = func;
}
/* Compute the number of unitids consumed. */
printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n",
dev_path(dev), count, static_count);
if (count < static_count)
count = static_count;
/* Update the unitid of the next device. */
ht_unitid_base[ht_dev_num] = next_unitid;
ht_dev_num++;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if (offset_unitid) {
real_last_pos = pos;
real_last_unitid = next_unitid;
real_last_dev = dev;
}
#endif
next_unitid += count;
if (next_unitid > max_unitid)
max_unitid = next_unitid;
/* Setup the hypertransport link. */
bus->reset_needed |= ht_setup_link(&prev, dev, pos);
printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n",
dev_path(dev), dev->vendor, dev->device,
(dev->enabled? "enabled" : "disabled"), next_unitid);
} while (last_unitid != next_unitid);
end_of_chain:
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if (offset_unitid && (ht_dev_num > 1)
&& (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE)
&& !end_used) {
u16 flags;
flags = pci_read_config16(real_last_dev,
real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_write_config16(real_last_dev,
real_last_pos + PCI_CAP_FLAGS, flags);
for (func = real_last_dev; func; func = func->sibling) {
func->path.pci.devfn -= ((real_last_unitid
- CONFIG_HT_CHAIN_END_UNITID_BASE) << 3);
last_func = func;
}
/* Update last one. */
ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE;
printk(BIOS_DEBUG, " unitid: %04x --> %04x\n",
real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE);
}
#endif
next_unitid = max_unitid;
if (next_unitid > 0x20)
next_unitid = 0x20;
if ((bus->secondary == 0) && (next_unitid > 0x18))
next_unitid = 0x18; /* Avoid K8 on bus 0. */
/*
* Die if any leftover static devices are are found. There's probably
* a problem in devicetree.cb.
*/
if (old_devices) {
struct device *left;
for (left = old_devices; left; left = left->sibling)
printk(BIOS_DEBUG, "%s\n", dev_path(left));
printk(BIOS_ERR, "HT: Leftover static devices. "
"Check your devicetree.cb\n");
/*
* Put back the leftover static device, and let pci_scan_bus()
* disable it.
*/
if (last_func && !last_func->sibling)
last_func->sibling = old_devices;
}
return next_unitid;
}
/**
* Scan a PCI bridge and the buses behind the bridge.
*
* Determine the existence of buses behind the bridge. Set up the bridge
* according to the result of the scan.
*
* This function is the default scan_bus() method for PCI bridge devices.
*
* @param bus TODO
* @param min_devfn TODO
* @param max_devfn TODO
*/
static void hypertransport_scan_chain_x(struct bus *bus,
unsigned int min_devfn, unsigned int max_devfn)
{
unsigned int ht_unitid_base[4];
unsigned int offset_unitid = 1;
unsigned int next_unitid = do_hypertransport_scan_chain(bus, min_devfn, max_devfn,
ht_unitid_base, offset_unitid);
/* Now that nothing is overlapping it is safe to scan the children. */
pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7);
}
static void ht_scan_bridge(struct device *dev)
{
do_pci_scan_bridge(dev, hypertransport_scan_chain_x);
}
/** Default device operations for hypertransport bridges */
static struct pci_operations ht_bus_ops_pci = {
.set_subsystem = 0,
};
struct device_operations default_ht_ops_bus = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.scan_bus = ht_scan_bridge,
.reset_bus = pci_bus_reset,
.ops_pci = &ht_bus_ops_pci,
};

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@@ -19,7 +19,6 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pcix.h> #include <device/pcix.h>
#include <device/pciexp.h> #include <device/pciexp.h>
#include <device/hypertransport.h>
#include <pc80/i8259.h> #include <pc80/i8259.h>
#include <security/vboot/vbnv.h> #include <security/vboot/vbnv.h>
#include <timestamp.h> #include <timestamp.h>
@@ -862,19 +861,6 @@ static struct device_operations *get_pci_bridge_ops(struct device *dev)
return &default_pcix_ops_bus; return &default_pcix_ops_bus;
} }
#endif #endif
#if CONFIG(HYPERTRANSPORT_PLUGIN_SUPPORT)
unsigned int htpos = 0;
while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) {
u16 flags;
flags = pci_read_config16(dev, htpos + PCI_CAP_FLAGS);
if ((flags >> 13) == 1) {
/* Host or Secondary Interface */
printk(BIOS_DEBUG, "%s subordinate bus HT\n",
dev_path(dev));
return &default_ht_ops_bus;
}
}
#endif
#if CONFIG(PCIEXP_PLUGIN_SUPPORT) #if CONFIG(PCIEXP_PLUGIN_SUPPORT)
unsigned int pciexpos; unsigned int pciexpos;
pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE);

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@@ -1,11 +0,0 @@
#ifndef DEVICE_HYPERTRANSPORT_H
#define DEVICE_HYPERTRANSPORT_H
#include <device/hypertransport_def.h>
extern struct device_operations default_ht_ops_bus;
#define HT_IO_HOST_ALIGN 4096
#define HT_MEM_HOST_ALIGN (1024*1024)
#endif /* DEVICE_HYPERTRANSPORT_H */

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@@ -1,28 +0,0 @@
#ifndef DEVICE_HYPERTRANSPORT_DEF_H
#define DEVICE_HYPERTRANSPORT_DEF_H
#define HT_FREQ_200Mhz 0
#define HT_FREQ_300Mhz 1
#define HT_FREQ_400Mhz 2
#define HT_FREQ_500Mhz 3
#define HT_FREQ_600Mhz 4
#define HT_FREQ_800Mhz 5
#define HT_FREQ_1000Mhz 6
#define HT_FREQ_1200Mhz 7
#define HT_FREQ_1400Mhz 8
#define HT_FREQ_1600Mhz 9
#define HT_FREQ_1800Mhz 10
#define HT_FREQ_2000Mhz 11
#define HT_FREQ_2200Mhz 12
#define HT_FREQ_2400Mhz 13
#define HT_FREQ_2600Mhz 14
#define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */
static inline bool offset_unit_id(bool is_sb_ht_chain)
{
bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1)
|| (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20);
return need_offset && is_sb_ht_chain;
}
#endif /* DEVICE_HYPERTRANSPORT_DEF_H */

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@@ -2777,6 +2777,9 @@
#define PCI_DID_INTEL_IBEXPEAK_HECI1 0x3b64 #define PCI_DID_INTEL_IBEXPEAK_HECI1 0x3b64
#define PCI_DID_INTEL_IBEXPEAK_THERMAL 0x3b32 #define PCI_DID_INTEL_IBEXPEAK_THERMAL 0x3b32
/* Intel SDMA device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_LP_SDMA 0x9c60
/* Intel LPC device ids */ /* Intel LPC device ids */
#define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41
#define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42
@@ -2989,6 +2992,21 @@
#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31 0x7a9f #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31 0x7a9f
/* Intel PCIE device ids */ /* Intel PCIE device ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1 0x8c10
#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP2 0x8c12
#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP3 0x8c14
#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP4 0x8c16
#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP5 0x8c18
#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP6 0x8c1a
#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP7 0x8c1c
#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP8 0x8c1e
#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP1 0x9c10
#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP2 0x9c12
#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP3 0x9c14
#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP4 0x9c16
#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP5 0x9c18
#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP6 0x9c1a
#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10
#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2 0x9d11 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2 0x9d11
#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3 0x9d12 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3 0x9d12
@@ -3268,6 +3286,23 @@
#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28 0x7acb #define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28 0x7acb
/* Intel SATA device Ids */ /* Intel SATA device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00
#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_AHCI 0x8c02
#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_1 0x8c04
#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM 0x8c06
#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45 0x8c08
#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_2 0x8c0e
#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE 0x8c01
#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_AHCI 0x8c03
#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_1 0x8c05
#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM 0x8c07
#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE_P45 0x8c09
#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_2 0x8c0f
#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_AHCI 0x9c03
#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_1 0x9c05
#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_PREM 0x9c07
#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_2 0x9c0f
#define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03
#define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07
#define PCI_DEVICE_ID_INTEL_SPT_KBL_SATA 0x282a #define PCI_DEVICE_ID_INTEL_SPT_KBL_SATA 0x282a
@@ -3337,6 +3372,8 @@
#define PCI_DEVICE_ID_INTEL_ADP_S_PMC 0x7aa1 #define PCI_DEVICE_ID_INTEL_ADP_S_PMC 0x7aa1
/* Intel I2C device Ids */ /* Intel I2C device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_LP_I2C0 0x9c61
#define PCI_DEVICE_ID_INTEL_LPT_LP_I2C1 0x9c62
#define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60
#define PCI_DEVICE_ID_INTEL_SPT_I2C1 0x9d61 #define PCI_DEVICE_ID_INTEL_SPT_I2C1 0x9d61
#define PCI_DEVICE_ID_INTEL_SPT_I2C2 0x9d62 #define PCI_DEVICE_ID_INTEL_SPT_I2C2 0x9d62
@@ -3428,6 +3465,8 @@
#define PCI_DEVICE_ID_INTEL_ADP_S_I2C5 0x7afd #define PCI_DEVICE_ID_INTEL_ADP_S_I2C5 0x7afd
/* Intel UART device Ids */ /* Intel UART device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_LP_UART0 0x9c63
#define PCI_DEVICE_ID_INTEL_LPT_LP_UART1 0x9c64
#define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27
#define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28 #define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28
#define PCI_DEVICE_ID_INTEL_SPT_UART2 0x9d66 #define PCI_DEVICE_ID_INTEL_SPT_UART2 0x9d66
@@ -3487,6 +3526,8 @@
#define PCI_DEVICE_ID_INTEL_ADP_S_UART6 0x7adf #define PCI_DEVICE_ID_INTEL_ADP_S_UART6 0x7adf
/* Intel SPI device Ids */ /* Intel SPI device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0 0x9c65
#define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI1 0x9c66
#define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24
#define PCI_DEVICE_ID_INTEL_SPT_SPI2 0x9d29 #define PCI_DEVICE_ID_INTEL_SPT_SPI2 0x9d29
#define PCI_DEVICE_ID_INTEL_SPT_SPI3 0x9d2a #define PCI_DEVICE_ID_INTEL_SPT_SPI3 0x9d2a
@@ -3786,6 +3827,8 @@
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f #define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f
/* Intel SMBUS device Ids */ /* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22
#define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22
#define PCI_DEVICE_ID_INTEL_APL_SMBUS 0x5ad4 #define PCI_DEVICE_ID_INTEL_APL_SMBUS 0x5ad4
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23
#define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123
@@ -3802,7 +3845,14 @@
#define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS 0xa0a3
#define PCI_DEVICE_ID_INTEL_ADP_S_SMBUS 0x7aa3 #define PCI_DEVICE_ID_INTEL_ADP_S_SMBUS 0x7aa3
/* Intel EHCI device IDs */
#define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_1 0x8c26
#define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_2 0x8c2d
#define PCI_DEVICE_ID_INTEL_LPT_LP_EHCI 0x9c26
/* Intel XHCI device Ids */ /* Intel XHCI device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_XHCI 0x8c31
#define PCI_DEVICE_ID_INTEL_LPT_LP_XHCI 0x9c31
#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
#define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8 #define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8
#define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f #define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f
@@ -3856,6 +3906,8 @@
#define PCI_DEVICE_ID_INTEL_ADP_S_SRAM 0x7aa7 #define PCI_DEVICE_ID_INTEL_ADP_S_SRAM 0x7aa7
/* Intel AUDIO device Ids */ /* Intel AUDIO device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_AUDIO 0x8c20
#define PCI_DEVICE_ID_INTEL_LPT_LP_AUDIO 0x9c20
#define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98
#define PCI_DEVICE_ID_INTEL_GLK_AUDIO 0x3198 #define PCI_DEVICE_ID_INTEL_GLK_AUDIO 0x3198
#define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8 #define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8
@@ -3883,6 +3935,8 @@
#define PCI_DEVICE_ID_INTEL_ADP_P_AUDIO 0x51c8 #define PCI_DEVICE_ID_INTEL_ADP_P_AUDIO 0x51c8
/* Intel HECI/ME device Ids */ /* Intel HECI/ME device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_MEI 0x8c3a
#define PCI_DEVICE_ID_INTEL_LPT_LP_MEI 0x9c3a
#define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a
#define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a #define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a
#define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0 #define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0
@@ -3932,6 +3986,7 @@
#define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1 #define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1
/* Intel SD device Ids */ /* Intel SD device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_LP_SD 0x9c35
#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
#define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d #define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d

View File

@@ -187,6 +187,7 @@ enum {
enum { enum {
NHLT_PDM_DEV, NHLT_PDM_DEV,
NHLT_PDM_DEV_CAVS15, // NHLT_PDM_DEV on cAVS1.5 (KBL) based platforms
}; };
/* Endpoint direction. */ /* Endpoint direction. */

View File

@@ -57,6 +57,7 @@ const char *smbios_processor_serial_number(void);
void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision); void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision);
unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo);
unsigned int smbios_processor_external_clock(void); unsigned int smbios_processor_external_clock(void);
unsigned int smbios_processor_characteristics(void); unsigned int smbios_processor_characteristics(void);
struct cpuid_result; struct cpuid_result;

View File

@@ -29,6 +29,24 @@ config AMD_LPC_DEBUG_CARD
PICASSO_CONSOLE_UART which selects the SoC's integrated memory-mapped PICASSO_CONSOLE_UART which selects the SoC's integrated memory-mapped
UART for coreboot console output. UART for coreboot console output.
choice
prompt "SMSC/Microchip 1036 SuperIO config address"
depends on SUPERIO_SMSC_SIO1036
default SMSC_SIO1036_BASE_164E
config SMSC_SIO1036_BASE_4E
bool "0x4e/0x4d base address"
config SMSC_SIO1036_BASE_164E
bool "0x164e/0x164d base address"
endchoice
config SUPERIO_ADDR_BASE
hex
default 0x4e if SMSC_SIO1036_BASE_4E
default 0x164e if SMSC_SIO1036_BASE_164E
config CBFS_SIZE config CBFS_SIZE
hex hex
default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP

View File

@@ -5,14 +5,19 @@
#include <superio/smsc/sio1036/sio1036.h> #include <superio/smsc/sio1036/sio1036.h>
#include "gpio.h" #include "gpio.h"
#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) #define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_ADDR_BASE, SIO1036_SP1)
void bootblock_mainboard_early_init(void) void bootblock_mainboard_early_init(void)
{ {
mainboard_program_early_gpios(); mainboard_program_early_gpios();
if (CONFIG(SUPERIO_SMSC_SIO1036)) { if (CONFIG(SUPERIO_SMSC_SIO1036)) {
lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F); if (CONFIG_SUPERIO_ADDR_BASE == 0x4e) {
lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F);
} else {
// set up 16 byte wide I/O range window for the super IO
lpc_set_wideio_range(CONFIG_SUPERIO_ADDR_BASE & ~0xF, 16);
}
lpc_enable_decode(DECODE_ENABLE_SERIAL_PORT0 << CONFIG_UART_FOR_CONSOLE); lpc_enable_decode(DECODE_ENABLE_SERIAL_PORT0 << CONFIG_UART_FOR_CONSOLE);
sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
} }

View File

@@ -21,7 +21,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -34,7 +34,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -47,7 +47,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -60,7 +60,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -73,7 +73,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x5, .tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -86,7 +86,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x5, .tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"

View File

@@ -21,7 +21,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -34,7 +34,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -47,7 +47,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -60,7 +60,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -73,7 +73,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x5, .tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -86,7 +86,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x5, .tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"

View File

@@ -18,7 +18,6 @@ entries
# coreboot config options: cpu # coreboot config options: cpu
# coreboot config options: northbridge # coreboot config options: northbridge
#432 5 e 11 gfx_uma_size #432 5 e 11 gfx_uma_size
#440 8 h 0 volume
# SandyBridge MRC Scrambler Seed values # SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed 896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3 928 32 r 0 mrc_scrambler_seed_s3

View File

@@ -28,10 +28,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <mainboard/gpio.h> #include <mainboard/gpio.h>
#include <soc/ramstage.h>
/* /*
* TODO: * TODO:
@@ -12,7 +12,11 @@
* - Make TBT port configurable (TBT <> DisplayPort) * - Make TBT port configurable (TBT <> DisplayPort)
*/ */
void mainboard_silicon_init_params(FSP_SIL_UPD *params) static void init_mainboard(void *chip_info)
{ {
mainboard_configure_gpios(); mainboard_configure_gpios();
} }
struct chip_operations mainboard_ops = {
.init = init_mainboard,
};

View File

@@ -26,10 +26,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -26,10 +26,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -28,10 +28,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -28,10 +28,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -11,7 +11,7 @@ config BOARD_GOOGLE_BASEBOARD_PUFF
select RT8168_SET_LED_MODE select RT8168_SET_LED_MODE
select ROMSTAGE_SPD_SMBUS select ROMSTAGE_SPD_SMBUS
select SPD_READ_BY_WORD select SPD_READ_BY_WORD
select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_LITE_SKU if CHROMEOS
select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_DPTF
select DPTF_USE_EISA_HID select DPTF_USE_EISA_HID

View File

@@ -28,10 +28,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -26,10 +26,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -26,10 +26,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -22,6 +22,8 @@ config BOARD_GOOGLE_LINDAR
select BOARD_GOOGLE_BASEBOARD_VOLTEER select BOARD_GOOGLE_BASEBOARD_VOLTEER
select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_LITE_SKU
select INTEL_CAR_NEM select INTEL_CAR_NEM
select CHROMEOS_DSM_CALIB
select DRIVERS_I2C_RT1011
config BOARD_GOOGLE_MALEFOR config BOARD_GOOGLE_MALEFOR
bool "-> Malefor" bool "-> Malefor"

View File

@@ -86,7 +86,8 @@ static void fw_config_handle(void *unused)
} }
if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) ||
fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) || fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) ||
fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)) ||
fw_config_probe(FW_CONFIG(AUDIO, RT1011_ALC5682I_I2S))) {
printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP3.\n"); printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP3.\n");
gpio_configure_pads(i2s_up3_enable_pads, ARRAY_SIZE(i2s_up3_enable_pads)); gpio_configure_pads(i2s_up3_enable_pads, ARRAY_SIZE(i2s_up3_enable_pads));
gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));

View File

@@ -16,6 +16,7 @@ fw_config
option MAX98373_ALC5682_SNDW 3 option MAX98373_ALC5682_SNDW 3
option MAX98373_ALC5682I_I2S_UP4 4 option MAX98373_ALC5682I_I2S_UP4 4
option MAX98360_ALC5682I_I2S 5 option MAX98360_ALC5682I_I2S 5
option RT1011_ALC5682I_I2S 6
end end
field TABLETMODE 11 field TABLETMODE 11
option TABLETMODE_DISABLED 0 option TABLETMODE_DISABLED 0
@@ -37,6 +38,9 @@ fw_config
option SD_ABSENT 0 option SD_ABSENT 0
option SD_GL9755S 1 option SD_GL9755S 1
option SD_RTS5261 2 option SD_RTS5261 2
option SD_RTS5227S 3
option SD_L9750 4
option SD_OZ711LV2LN 5
end end
field KB_LAYOUT 20 21 field KB_LAYOUT 20 21
option KB_LAYOUT_DEFAULT 0 option KB_LAYOUT_DEFAULT 0

View File

@@ -58,12 +58,22 @@ chip soc/intel/tigerlake
}, },
}, },
}" }"
#These settings improve the USB2 Port1 eye diagram
#Disable Type-A Port A1
register "usb2_ports[1]" = "USB2_PORT_EMPTY"
#Disable M.2 WWAN
register "usb2_ports[2]" = "USB2_PORT_EMPTY"
#improve the USB2 Port1 eye diagram
register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)"
#lower camera driving
register "usb2_ports[4]" = "{ register "usb2_ports[4]" = "{
.enable = 1, .enable = 1,
.tx_bias = 7, .tx_bias = 0,
.tx_emp_enable = 7, .tx_emp_enable = 0,
.pre_emp_bias = 3, .pre_emp_bias = 0,
.pre_emp_bit = 0, .pre_emp_bit = 0,
}" }"

View File

@@ -5,3 +5,4 @@ SPD_SOURCES =
SPD_SOURCES += ddr4-spd-2.hex # ID = 0(0b0000) Parts = H5ANAG6NCMR-XNC SPD_SOURCES += ddr4-spd-2.hex # ID = 0(0b0000) Parts = H5ANAG6NCMR-XNC
SPD_SOURCES += ddr4-spd-7.hex # ID = 1(0b0001) Parts = MT40A1G16KD-062E:E, K4AAG165WA-BCWE SPD_SOURCES += ddr4-spd-7.hex # ID = 1(0b0001) Parts = MT40A1G16KD-062E:E, K4AAG165WA-BCWE
SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = H5AN8G6NDJR-XNC, MT40A512M16TB-062E:J, K4A8G165WC-BCWE SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = H5AN8G6NDJR-XNC, MT40A512M16TB-062E:J, K4A8G165WC-BCWE
SPD_SOURCES += ddr4-spd-9.hex # ID = 3(0b0011) Parts = H5ANAG6NCJR-XNC

View File

@@ -5,3 +5,4 @@ K4AAG165WA-BCWE 1 (0001)
H5AN8G6NDJR-XNC 2 (0010) H5AN8G6NDJR-XNC 2 (0010)
MT40A512M16TB-062E:J 2 (0010) MT40A512M16TB-062E:J 2 (0010)
K4A8G165WC-BCWE 2 (0010) K4A8G165WC-BCWE 2 (0010)
H5ANAG6NCJR-XNC 3 (0011)

View File

@@ -4,3 +4,4 @@ K4AAG165WA-BCWE
H5AN8G6NDJR-XNC H5AN8G6NDJR-XNC
MT40A512M16TB-062E:J MT40A512M16TB-062E:J
K4A8G165WC-BCWE K4A8G165WC-BCWE
H5ANAG6NCJR-XNC

View File

@@ -35,7 +35,25 @@ chip soc/intel/tigerlake
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1" register "property_list[0].integer" = "1"
device i2c 1a on end device i2c 1a on
probe AUDIO RT1011_ALC5682I_I2S
end
end
chip drivers/i2c/rt1011
register "desc" = ""Realtek SPK AMP L""
register "uid" = "0"
register "name" = ""RTL""
device i2c 38 on
probe AUDIO RT1011_ALC5682I_I2S
end
end
chip drivers/i2c/rt1011
register "desc" = ""Realtek SPK AMP R""
register "uid" = "1"
register "name" = ""RTR""
device i2c 39 on
probe AUDIO RT1011_ALC5682I_I2S
end
end end
end end
device ref i2c1 on device ref i2c1 on

View File

@@ -23,22 +23,22 @@ chip soc/intel/tigerlake
## Active Policy ## Active Policy
register "policies.active" = "{ register "policies.active" = "{
[0] = {.target = DPTF_CPU, [0] = {.target = DPTF_CPU,
.thresholds = {TEMP_PCT(94, 100),}}, .thresholds = {TEMP_PCT(98, 100),}},
[1] = {.target = DPTF_TEMP_SENSOR_2, [1] = {.target = DPTF_TEMP_SENSOR_2,
.thresholds = {TEMP_PCT(64, 100), .thresholds = {TEMP_PCT(64, 100),
TEMP_PCT(60, 90), TEMP_PCT(60, 90),
TEMP_PCT(56, 80), TEMP_PCT(56, 80),
TEMP_PCT(52, 70), TEMP_PCT(52, 70),
TEMP_PCT(48, 60), TEMP_PCT(47, 60),
TEMP_PCT(44, 50), TEMP_PCT(42, 50),
TEMP_PCT(40, 40),}}}" TEMP_PCT(35, 40),}}}"
## Passive Policy ## Passive Policy
register "policies.passive" = "{ register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 52, 6000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}"
## Critical Policy ## Critical Policy
@@ -58,7 +58,7 @@ chip soc/intel/tigerlake
.time_window_min = 28 * MSECS_PER_SEC, .time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}, .granularity = 200,},
.pl2 = {.min_power = 15000, .pl2 = {.min_power = 51000,
.max_power = 51000, .max_power = 51000,
.time_window_min = 28 * MSECS_PER_SEC, .time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC,

View File

@@ -64,7 +64,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -77,7 +77,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -90,7 +90,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -103,7 +103,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -116,7 +116,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x5, .tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -129,7 +129,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x5, .tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"

View File

@@ -64,7 +64,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -77,7 +77,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -90,7 +90,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -103,7 +103,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x6, .tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -116,7 +116,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x5, .tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -129,7 +129,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02, .tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x5, .tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"

View File

@@ -30,7 +30,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0xf, .tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -42,7 +42,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0xf, .tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -54,7 +54,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0xf, .tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -66,7 +66,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0xf, .tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"

View File

@@ -37,7 +37,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x9, .tx_vref_tune = 0x9,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -49,7 +49,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0x9, .tx_vref_tune = 0x9,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"

View File

@@ -43,7 +43,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0xf, .tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"

View File

@@ -30,7 +30,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0xf, .tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"
@@ -42,7 +42,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0, .tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1, .tx_rise_tune = 0x1,
.rx_vref_tune = 0xf, .tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3, .tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01, .tx_res_tune = 0x01,
}" }"

View File

@@ -28,8 +28,6 @@ entries
# coreboot config options: northbridge # coreboot config options: northbridge
432 3 e 11 gfx_uma_size 432 3 e 11 gfx_uma_size
440 8 h 0 volume
# SandyBridge MRC Scrambler Seed values # SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed 896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3 928 32 r 0 mrc_scrambler_seed_s3

View File

@@ -28,10 +28,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -28,10 +28,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -28,10 +28,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -26,10 +26,6 @@ entries
#Used by ChromeOS: #Used by ChromeOS:
416 128 r 0 vbnv 416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum

View File

@@ -1,9 +1,11 @@
## SPDX-License-Identifier: GPL-2.0-only ## SPDX-License-Identifier: GPL-2.0-only
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
bootblock-y += bootblock.c bootblock-y += bootblock.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-y += gpio.c
ramstage-y += ramstage.c ramstage-y += ramstage.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads

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@@ -1,14 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H #include <mainboard/gpio.h>
#define MAINBOARD_GPIO_H
#include <soc/gpe.h> #include <soc/gpe.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#ifndef __ACPI__
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),
PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1),
@@ -225,6 +220,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1),
}; };
#endif void mainboard_configure_gpios(void)
{
#endif gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
void mainboard_configure_gpios(void);
#endif

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@@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include "gpio.h" #include <mainboard/gpio.h>
void mainboard_silicon_init_params(FSP_SIL_UPD *params) void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{ {
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); mainboard_configure_gpios();
} }

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@@ -8,8 +8,7 @@
#include <soc/romstage.h> #include <soc/romstage.h>
#include <fsp/soc_binding.h> #include <fsp/soc_binding.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <variant.h>
#include "variant.h"
/* Rcomp resistor */ /* Rcomp resistor */
static const u16 rcomp_resistors[3] = { 121, 75, 100 }; static const u16 rcomp_resistors[3] = { 121, 75, 100 };

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@@ -5,8 +5,7 @@
#include <console/console.h> #include <console/console.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <fsp/soc_binding.h> #include <fsp/soc_binding.h>
#include <variant.h>
#include "../../variant.h"
void variant_memory_init_params(FSPM_UPD *const mupd) void variant_memory_init_params(FSPM_UPD *const mupd)
{ {

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@@ -1,8 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <fsp/soc_binding.h> #include <fsp/soc_binding.h>
#include <variant.h>
#include "../../variant.h"
void variant_memory_init_params(FSPM_UPD *const mupd) void variant_memory_init_params(FSPM_UPD *const mupd)
{ {

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@@ -26,6 +26,31 @@
extern struct fru_info_str fru_strings; extern struct fru_info_str fru_strings;
static char slot_id_str[SLOT_ID_LEN]; static char slot_id_str[SLOT_ID_LEN];
/* Override SMBIOS type 16 error correction type. */
unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo)
{
const struct SystemMemoryMapHob *hob;
hob = get_system_memory_map();
assert(hob != NULL);
switch (hob->RasModesEnabled) {
case CH_INDEPENDENT:
return MEMORY_ARRAY_ECC_SINGLE_BIT;
case FULL_MIRROR_1LM:
case PARTIAL_MIRROR_1LM:
case FULL_MIRROR_2LM:
case PARTIAL_MIRROR_2LM:
return MEMORY_ARRAY_ECC_MULTI_BIT;
case RK_SPARE:
return MEMORY_ARRAY_ECC_SINGLE_BIT;
case CH_LOCKSTEP:
return MEMORY_ARRAY_ECC_SINGLE_BIT;
default:
return MEMORY_ARRAY_ECC_MULTI_BIT;
}
}
/* /*
* Update SMBIOS type 0 ec version. * Update SMBIOS type 0 ec version.
* In deltalake, BMC version is used to represent ec version. * In deltalake, BMC version is used to represent ec version.

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@@ -3,7 +3,7 @@
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <stdint.h> #include <stdint.h>
#include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/nb_common.h>
#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/common/amd_pci_util.h>
static void *smp_write_config_table(void *v) static void *smp_write_config_table(void *v)

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@@ -15,8 +15,6 @@ entries
# coreboot config options: console # coreboot config options: console
395 4 e 6 debug_level 395 4 e 6 debug_level
400 8 h 0 volume
# coreboot config options: southbridge # coreboot config options: southbridge
408 1 e 1 nmi 408 1 e 1 nmi
409 2 e 7 power_on_after_fail 409 2 e 7 power_on_after_fail

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@@ -8,13 +8,12 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/hypertransport.h>
#include <string.h> #include <string.h>
#include <lib.h> #include <lib.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/amd/msr.h> #include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/nb_common.h> #include <northbridge/amd/nb_common.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#include <sb_cimx.h> #include <sb_cimx.h>

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@@ -8,7 +8,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/hypertransport.h>
#include <string.h> #include <string.h>
#include <lib.h> #include <lib.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
@@ -19,7 +18,7 @@
#include <Porting.h> #include <Porting.h>
#include <Options.h> #include <Options.h>
#include <Topology.h> #include <Topology.h>
#include <northbridge/amd/agesa/nb_common.h> #include <northbridge/amd/nb_common.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>

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@@ -7,11 +7,25 @@
#define BUS0 0 #define BUS0 0
/* GNB Root Complex */
#define GNB_DEV 0x0
#define GNB_FUNC 0
#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)
/* IOMMU */
#define IOMMU_DEV 0x0
#define IOMMU_FUNC 2
#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)
/* Graphics and Display */ /* Graphics and Display */
#define GFX_DEV 0x1 #define GFX_DEV 0x1
#define GFX_FUNC 0 #define GFX_FUNC 0
#define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC) #define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC)
/* Integrated GPU Internal HDMI Audio Controller */
#define ACTL_FUNC 1
#define ACTL_DEVFN PCI_DEVFN(GFX_DEV,ACTL_FUNC)
/* PCIe Ports */ /* PCIe Ports */
#define NB_PCIE_PORT1_DEV 0x2 #define NB_PCIE_PORT1_DEV 0x2
#define NB_PCIE_PORT2_DEV 0x3 #define NB_PCIE_PORT2_DEV 0x3

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@@ -8,7 +8,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/hypertransport.h>
#include <string.h> #include <string.h>
#include <lib.h> #include <lib.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
@@ -19,7 +18,7 @@
#include <AGESA.h> #include <AGESA.h>
#include <Options.h> #include <Options.h>
#include <Topology.h> #include <Topology.h>
#include <northbridge/amd/agesa/nb_common.h> #include <northbridge/amd/nb_common.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>

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@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __AMD_NB_COMMON_H__
#define __AMD_NB_COMMON_H__
#define DEV_CDB 0x18
#endif

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@@ -3,6 +3,9 @@
#ifndef __AMD_NB_COMMON_H__ #ifndef __AMD_NB_COMMON_H__
#define __AMD_NB_COMMON_H__ #define __AMD_NB_COMMON_H__
#define HT_IO_HOST_ALIGN 4096
#define HT_MEM_HOST_ALIGN (1024 * 1024)
#define DEV_CDB 0x18 #define DEV_CDB 0x18
#define IO_APIC2_ADDR 0xfec20000 #define IO_APIC2_ADDR 0xfec20000

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@@ -7,7 +7,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/hypertransport.h>
#include <string.h> #include <string.h>
#include <lib.h> #include <lib.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
@@ -18,7 +17,7 @@
#include <cpu/amd/msr.h> #include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#define MAX_NODE_NUMS MAX_NODES #define MAX_NODE_NUMS MAX_NODES

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@@ -10,7 +10,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/hypertransport.h>
#include <string.h> #include <string.h>
#include <stdlib.h> #include <stdlib.h>
#include <lib.h> #include <lib.h>
@@ -22,7 +21,7 @@
#include <cpu/amd/msr.h> #include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#include <southbridge/amd/pi/hudson/pci_devs.h> #include <southbridge/amd/pi/hudson/pci_devs.h>

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@@ -8,7 +8,7 @@
#include <device/device.h> #include <device/device.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/nb_common.h>
void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{ {

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@@ -30,7 +30,7 @@ struct __packed usb2_phy_tune {
/* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */ /* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */
uint8_t tx_rise_tune; uint8_t tx_rise_tune;
/* HS DC Voltage Level Adjustment. Range 0 - 0xF */ /* HS DC Voltage Level Adjustment. Range 0 - 0xF */
uint8_t rx_vref_tune; uint8_t tx_vref_tune;
/* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */ /* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */
uint8_t tx_hsxv_tune; uint8_t tx_hsxv_tune;
/* USB Source Impedance Adjustment. Range 0 - 0x3. */ /* USB Source Impedance Adjustment. Range 0 - 0x3. */

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@@ -246,6 +246,4 @@ struct pei_data {
struct pei_memory_info meminfo; struct pei_memory_info meminfo;
} __packed; } __packed;
typedef struct pei_data PEI_DATA;
#endif #endif

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@@ -28,6 +28,4 @@ struct pei_data {
int data_to_save_size; int data_to_save_size;
} __packed; } __packed;
typedef struct pei_data PEI_DATA;
#endif /* _PEI_WRAPPER_H_ */ #endif /* _PEI_WRAPPER_H_ */

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@@ -161,6 +161,12 @@ config SKYLAKE_SOC_PCH_H
help help
Choose this option if you have a PCH-H chipset. Choose this option if you have a PCH-H chipset.
config NHLT_DMIC_1CH
bool
default n
help
Include DSP firmware settings for 1 channel DMIC array.
config NHLT_DMIC_2CH config NHLT_DMIC_2CH
bool bool
default n default n

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@@ -15,6 +15,7 @@ else
NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/skylake/nhlt-blobs NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/skylake/nhlt-blobs
endif endif
DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin
DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin
DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin
DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin
@@ -31,6 +32,10 @@ SSM4567_RENDER = ssm4567-render-2ch-48khz-24b.bin
SSM4567_CAPTURE = ssm4567-capture-4ch-48khz-32b.bin SSM4567_CAPTURE = ssm4567-capture-4ch-48khz-32b.bin
DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin
cbfs-files-$(CONFIG_NHLT_DMIC_1CH) += $(DMIC_1CH_48KHZ_16B)
$(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B)
$(DMIC_1CH_48KHZ_16B)-type := raw
cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B)
$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B)
$(DMIC_2CH_48KHZ_16B)-type := raw $(DMIC_2CH_48KHZ_16B)-type := raw

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@@ -2,6 +2,39 @@
#include <soc/nhlt.h> #include <soc/nhlt.h>
static const struct nhlt_format_config dmic_1ch_formats[] = {
/* 48 KHz 16-bits per sample. */
{
.num_channels = 1,
.sample_freq_khz = 48,
.container_bits_per_sample = 16,
.valid_bits_per_sample = 16,
.speaker_mask = SPEAKER_FRONT_CENTER,
.settings_file = "dmic-1ch-48khz-16b.bin",
},
};
static const struct nhlt_dmic_array_config dmic_1ch_mic_config = {
.tdm_config = {
.config_type = NHLT_TDM_BASIC,
},
.array_type = NHLT_MIC_ARRAY_VENDOR_DEFINED,
};
static const struct nhlt_endp_descriptor dmic_1ch_descriptors[] = {
{
.link = NHLT_LINK_PDM,
.device = NHLT_PDM_DEV_CAVS15,
.direction = NHLT_DIR_CAPTURE,
.vid = NHLT_VID,
.did = NHLT_DID_DMIC,
.cfg = &dmic_1ch_mic_config,
.cfg_size = sizeof(dmic_1ch_mic_config),
.formats = dmic_1ch_formats,
.num_formats = ARRAY_SIZE(dmic_1ch_formats),
},
};
static const struct nhlt_format_config dmic_2ch_formats[] = { static const struct nhlt_format_config dmic_2ch_formats[] = {
/* 48 KHz 16-bits per sample. */ /* 48 KHz 16-bits per sample. */
{ {
@@ -33,7 +66,7 @@ static const struct nhlt_dmic_array_config dmic_2ch_mic_config = {
static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = { static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = {
{ {
.link = NHLT_LINK_PDM, .link = NHLT_LINK_PDM,
.device = NHLT_PDM_DEV, .device = NHLT_PDM_DEV_CAVS15,
.direction = NHLT_DIR_CAPTURE, .direction = NHLT_DIR_CAPTURE,
.vid = NHLT_VID, .vid = NHLT_VID,
.did = NHLT_DID_DMIC, .did = NHLT_DID_DMIC,
@@ -77,7 +110,7 @@ static const struct nhlt_dmic_array_config dmic_4ch_mic_config = {
static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = { static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = {
{ {
.link = NHLT_LINK_PDM, .link = NHLT_LINK_PDM,
.device = NHLT_PDM_DEV, .device = NHLT_PDM_DEV_CAVS15,
.direction = NHLT_DIR_CAPTURE, .direction = NHLT_DIR_CAPTURE,
.vid = NHLT_VID, .vid = NHLT_VID,
.did = NHLT_DID_DMIC, .did = NHLT_DID_DMIC,
@@ -91,6 +124,9 @@ static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = {
int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels)
{ {
switch (num_channels) { switch (num_channels) {
case 1:
return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors,
ARRAY_SIZE(dmic_1ch_descriptors));
case 2: case 2:
return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors,
ARRAY_SIZE(dmic_2ch_descriptors)); ARRAY_SIZE(dmic_2ch_descriptors));

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@@ -50,13 +50,22 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_P2SB
select SOC_INTEL_COMMON_BLOCK_PMC
select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_TCO
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER
select UDELAY_TSC select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select MICROCODE_BLOB_NOT_HOOKED_UP select MICROCODE_BLOB_NOT_HOOKED_UP
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select FSP_CAR select FSP_CAR
select NO_SMM select CPU_INTEL_COMMON_SMM
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SMM_TSEG
select HAVE_SMI_HANDLER
select X86_SMM_LOADER_VERSION2
select REG_SCRIPT
config MAINBOARD_USES_FSP2_0 config MAINBOARD_USES_FSP2_0
bool bool

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@@ -12,6 +12,8 @@ ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c ch
ramstage-y += memmap.c pch.c ramstage-y += memmap.c pch.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c pmc.c
postcar-y += spi.c postcar-y += spi.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include

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@@ -78,6 +78,10 @@ config FSP_TEMP_RAM_SIZE
documentation says this needs to be at least 128KiB, but practice documentation says this needs to be at least 128KiB, but practice
show this needs to be 256KiB or more. show this needs to be 256KiB or more.
config IED_REGION_SIZE
hex
default 0x400000
config SOC_INTEL_COMMON_BLOCK_P2SB config SOC_INTEL_COMMON_BLOCK_P2SB
def_bool y def_bool y

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@@ -5,6 +5,7 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y)
subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/intel/turbo
subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/lapic
subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/mtrr
subdirs-y += ../../../../cpu/x86/smm
subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/x86/tsc
subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/microcode

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@@ -7,7 +7,9 @@
#include <console/debug.h> #include <console/debug.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/intel/common/common.h> #include <cpu/intel/common/common.h>
#include <cpu/intel/em64t101_save_state.h>
#include <cpu/intel/microcode.h> #include <cpu/intel/microcode.h>
#include <cpu/intel/smm_reloc.h>
#include <cpu/intel/turbo.h> #include <cpu/intel/turbo.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/x86/mp.h> #include <cpu/x86/mp.h>
@@ -17,6 +19,7 @@
#include <soc/cpu.h> #include <soc/cpu.h>
#include <soc/msr.h> #include <soc/msr.h>
#include <soc/soc_util.h> #include <soc/soc_util.h>
#include <soc/smmrelocate.h>
#include <soc/util.h> #include <soc/util.h>
#include "chip.h" #include "chip.h"
@@ -172,16 +175,16 @@ static void post_mp_init(void)
/* Set Max Ratio */ /* Set Max Ratio */
set_max_turbo_freq(); set_max_turbo_freq();
/* if (CONFIG(HAVE_SMI_HANDLER))
* TODO: Now that all APs have been relocated as well as the BSP let SMIs global_smi_enable();
* start flowing.
*/
if (0) global_smi_enable();
} }
static const struct mp_ops mp_ops = { static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init, .pre_mp_init = pre_mp_init,
.get_cpu_count = get_thread_count, .get_cpu_count = get_thread_count,
.get_smm_info = get_smm_info,
.pre_mp_smm_init = smm_initialize,
.relocation_handler = smm_relocation_handler,
.get_microcode_info = get_microcode_info, .get_microcode_info = get_microcode_info,
.post_mp_init = post_mp_init, .post_mp_init = post_mp_init,
}; };

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@@ -102,10 +102,12 @@
#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
#define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_LPC _PCH_DEV(LPC, 0)
#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) #define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
#define PCH_DEV_PMC _PCH_DEV(LPC, 2) #define PCH_DEV_PMC _PCH_DEV(LPC, 2)
#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
#define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define PCH_DEV_SPI _PCH_DEV(LPC, 5)
#define HPET_BUS_NUM 0x0 #define HPET_BUS_NUM 0x0

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@@ -8,10 +8,13 @@
/* TODO - this requires xeon sp, server board support */ /* TODO - this requires xeon sp, server board support */
/* NOTE: We do not use intelblocks/nvs.h since it includes /* NOTE: We do not use intelblocks/nvs.h since it includes
mostly client specific attributes */ mostly client specific attributes */
/* TODO: This is not aligned with the ACPI asl code */
struct __packed global_nvs { struct __packed global_nvs {
uint8_t pcnt; /* 0x00 - Processor Count */ uint8_t pcnt; /* 0x00 - Processor Count */
uint32_t cbmc; /* 0x01 - coreboot memconsole */ uint32_t cbmc; /* 0x01 - coreboot memconsole */
uint8_t rsvd3[251]; uint8_t uior;
uint8_t rsvd3[250];
}; };
#endif /* _SOC_NVS_H_ */ #endif /* _SOC_NVS_H_ */

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@@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_SMBUS_H_
#define _SOC_SMBUS_H_
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO_STS_SECOND_TO (1 << 1)
#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
#define TCO2_CNT 0x0A
#define TCO_INTRD_SEL_MASK (3 << 1)
#define TCO_INTRD_SEL_SMI (1 << 2)
#define TCO_INTRD_SEL_INT (1 << 1)
/* SMBus I/O bits. */
#define SMBUS_SLAVE_ADDR 0x24
#endif

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@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _SOC_SMMRELOCATE_H_
#define _SOC_SMMRELOCATE_H_
void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size);
#endif

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@@ -193,3 +193,25 @@ const char *const *soc_smi_sts_array(size_t *smi_arr)
*smi_arr = ARRAY_SIZE(smi_sts_bits); *smi_arr = ARRAY_SIZE(smi_sts_bits);
return smi_sts_bits; return smi_sts_bits;
} }
const char *const *soc_tco_sts_array(size_t *tco_arr)
{
static const char *const tco_sts_bits[] = {
[0] = "NMI2SMI",
[1] = "OS_TCO",
[2] = "TCO_INT",
[3] = "TIMEOUT",
[7] = "NEWCENTURY",
[8] = "BIOSWR",
[9] = "CPUSCI",
[10] = "CPUSMI",
[12] = "CPUSERR",
[13] = "SLVSEL",
[16] = "INTRD_DET",
[17] = "SECOND_TO",
[20] = "SMLINK_SLV"
};
*tco_arr = ARRAY_SIZE(tco_sts_bits);
return tco_sts_bits;
}

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@@ -59,4 +59,8 @@ config HEAP_SIZE
hex hex
default 0x80000 default 0x80000
config IED_REGION_SIZE
hex
default 0x400000
endif endif

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@@ -8,7 +8,7 @@ subdirs-y += ../../../../cpu/x86/lapic
subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/mtrr
subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/x86/tsc
subdirs-y += ../../../../cpu/x86/cache subdirs-y += ../../../../cpu/x86/cache
subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../../cpu/x86/smm
postcar-y += soc_util.c postcar-y += soc_util.c

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@@ -10,9 +10,13 @@
#include <soc/msr.h> #include <soc/msr.h>
#include <soc/cpu.h> #include <soc/cpu.h>
#include <soc/soc_util.h> #include <soc/soc_util.h>
#include <soc/smmrelocate.h>
#include <soc/util.h> #include <soc/util.h>
#include <assert.h> #include <assert.h>
#include "chip.h" #include "chip.h"
#include <cpu/intel/smm_reloc.h>
#include <cpu/intel/em64t101_save_state.h>
static const config_t *chip_config = NULL; static const config_t *chip_config = NULL;
@@ -197,11 +201,8 @@ static void post_mp_init(void)
/* Set Max Ratio */ /* Set Max Ratio */
set_max_turbo_freq(); set_max_turbo_freq();
/* if (CONFIG(HAVE_SMI_HANDLER))
* TODO: Now that all APs have been relocated as well as the BSP let SMIs global_smi_enable();
* start flowing.
*/
if (0) global_smi_enable();
} }
/* /*
@@ -214,12 +215,9 @@ static void post_mp_init(void)
static const struct mp_ops mp_ops = { static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init, .pre_mp_init = pre_mp_init,
.get_cpu_count = get_platform_thread_count, .get_cpu_count = get_platform_thread_count,
//.get_smm_info = get_smm_info, /* TODO */ .get_smm_info = get_smm_info,
.get_smm_info = NULL, .pre_mp_smm_init = smm_initialize,
//.pre_mp_smm_init = southcluster_smm_clear_state, /* TODO */ .relocation_handler = smm_relocation_handler,
.pre_mp_smm_init = NULL,
//.relocation_handler = relocation_handler, /* TODO */
.relocation_handler = NULL,
.post_mp_init = post_mp_init, .post_mp_init = post_mp_init,
}; };

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@@ -141,10 +141,12 @@
#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
#define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_LPC _PCH_DEV(LPC, 0)
#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) #define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
#define PCH_DEV_PMC _PCH_DEV(LPC, 2) #define PCH_DEV_PMC _PCH_DEV(LPC, 2)
#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
#define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define PCH_DEV_SPI _PCH_DEV(LPC, 5)
#define CBDMA_DEV_NUM 0x04 #define CBDMA_DEV_NUM 0x04

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@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/smihandler.h>
#include <soc/pm.h>
#include <cpu/x86/smm.h>
/* This is needed by common SMM code */
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
[APM_STS_BIT] = smihandler_southbridge_apmc,
[PM1_STS_BIT] = smihandler_southbridge_pm1,
#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
[TCO_STS_BIT] = smihandler_southbridge_tco,
#endif
};

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@@ -0,0 +1,144 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <assert.h>
#include <string.h>
#include <cpu/x86/mp.h>
#include <cpu/intel/em64t101_save_state.h>
#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <smp/node.h>
#include <soc/msr.h>
#include <soc/smmrelocate.h>
static void fill_in_relocation_params(struct smm_relocation_params *params)
{
uintptr_t tseg_base;
size_t tseg_size;
smm_region(&tseg_base, &tseg_size);
if (!IS_ALIGNED(tseg_base, tseg_size)) {
/*
* Note SMRR2 is supported which might support base/size combinations.
* For now it looks like FSP-M always uses aligned base/size, so let's
* not care about that.
*/
printk(BIOS_WARNING,
"TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
return;
}
/* SMRR has 32-bits of valid address aligned to 4KiB. */
if (!IS_ALIGNED(tseg_size, 4 * KiB)) {
printk(BIOS_WARNING,
"TSEG size not aligned to the minimum 4KiB! Not setting SMRR\n");
return;
}
smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
params->smrr_base.lo = tseg_base | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
params->smrr_mask.lo = ~(tseg_size - 1) | MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0;
}
static void setup_ied_area(struct smm_relocation_params *params)
{
char *ied_base;
const struct ied_header ied = {
.signature = "INTEL RSVD",
.size = params->ied_size,
.reserved = {0},
};
ied_base = (void *)params->ied_base;
printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base);
printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size);
/* Place IED header at IEDBASE. */
memcpy(ied_base, &ied, sizeof(ied));
assert(params->ied_size > 1 * MiB + 32 * KiB);
/* Zero out 32KiB at IEDBASE + 1MiB */
memset(ied_base + 1 * MiB, 0, 32 * KiB);
}
void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
fill_in_relocation_params(&smm_reloc_params);
smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
if (smm_reloc_params.ied_size)
setup_ied_area(&smm_reloc_params);
*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
struct smm_relocation_params *relo_params)
{
u32 smbase;
u32 iedbase;
int apic_id;
em64t101_smm_state_save_area_t *save_state;
/*
* The relocated handler runs with all CPUs concurrently. Therefore
* stagger the entry points adjusting SMBASE downwards by save state
* size * CPU num.
*/
smbase = staggered_smbase;
iedbase = relo_params->ied_base;
apic_id = cpuid_ebx(1) >> 24;
printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n apic_id=0x%x\n",
smbase, iedbase, apic_id);
save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state));
save_state->smbase = smbase;
save_state->iedbase = iedbase;
}
/*
* The relocation work is actually performed in SMM context, but the code
* resides in the ramstage module. This occurs by trampolining from the default
* SMRAM entry point to here.
*/
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase)
{
msr_t mtrr_cap;
struct smm_relocation_params *relo_params = &smm_reloc_params;
printk(BIOS_DEBUG, "%s : CPU %d\n", __func__, cpu);
/* Make appropriate changes to the save state map. */
update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
/* Write SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED)
write_smrr(relo_params);
}
void smm_initialize(void)
{
/* Clear the SMM state in the southbridge. */
smm_southbridge_clear_state();
/* Run the relocation handler for on the BSP . */
smm_initiate_relocation();
}
void smm_relocate(void)
{
/* Save states via MSR does not seem to be supported on CPX */
if (!boot_cpu())
smm_initiate_relocation();
}

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@@ -132,7 +132,11 @@ static struct device_operations azalia_ops = {
.ops_pci = &pci_dev_ops_pci, .ops_pci = &pci_dev_ops_pci,
}; };
static const unsigned short pci_device_ids[] = { 0x8c20, 0x9c20, 0 }; static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_LPT_H_AUDIO,
PCI_DEVICE_ID_INTEL_LPT_LP_AUDIO,
0
};
static const struct pci_driver pch_azalia __pci_driver = { static const struct pci_driver pch_azalia __pci_driver = {
.ops = &azalia_ops, .ops = &azalia_ops,

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@@ -787,26 +787,27 @@ static struct device_operations device_ops = {
/* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */ /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
0x8c41, /* Mobile Full Featured Engineering Sample. */ PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE,
0x8c42, /* Desktop Full Featured Engineering Sample. */ PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE,
0x8c44, /* Z87 SKU */ PCI_DEVICE_ID_INTEL_LPT_Z87,
0x8c46, /* Z85 SKU */ PCI_DEVICE_ID_INTEL_LPT_Z85,
0x8c49, /* HM86 SKU */ PCI_DEVICE_ID_INTEL_LPT_HM86,
0x8c4a, /* H87 SKU */ PCI_DEVICE_ID_INTEL_LPT_H87,
0x8c4b, /* HM87 SKU */ PCI_DEVICE_ID_INTEL_LPT_HM87,
0x8c4c, /* Q85 SKU */ PCI_DEVICE_ID_INTEL_LPT_Q85,
0x8c4e, /* Q87 SKU */ PCI_DEVICE_ID_INTEL_LPT_Q87,
0x8c4f, /* QM87 SKU */ PCI_DEVICE_ID_INTEL_LPT_QM87,
0x8c50, /* B85 SKU */ PCI_DEVICE_ID_INTEL_LPT_B85,
0x8c52, /* C222 SKU */ PCI_DEVICE_ID_INTEL_LPT_C222,
0x8c54, /* C224 SKU */ PCI_DEVICE_ID_INTEL_LPT_C224,
0x8c56, /* C226 SKU */ PCI_DEVICE_ID_INTEL_LPT_C226,
0x8c5c, /* H81 SKU */ PCI_DEVICE_ID_INTEL_LPT_H81,
0x9c41, /* LP Full Featured Engineering Sample */ PCI_DEVICE_ID_INTEL_LPT_LP_SAMPLE,
0x9c43, /* LP Premium SKU */ PCI_DEVICE_ID_INTEL_LPT_LP_PREMIUM,
0x9c45, /* LP Mainstream SKU */ PCI_DEVICE_ID_INTEL_LPT_LP_MAINSTREAM,
0x9c47, /* LP Value SKU */ PCI_DEVICE_ID_INTEL_LPT_LP_VALUE,
0 }; 0
};
static const struct pci_driver pch_lpc __pci_driver = { static const struct pci_driver pch_lpc __pci_driver = {
.ops = &device_ops, .ops = &device_ops,

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@@ -836,8 +836,8 @@ static struct device_operations device_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
0x8c3a, /* Mobile */ PCI_DEVICE_ID_INTEL_LPT_H_MEI,
0x9c3a, /* Low Power */ PCI_DEVICE_ID_INTEL_LPT_LP_MEI,
0 0
}; };

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@@ -749,10 +749,20 @@ static struct device_operations device_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
/* Lynxpoint Mobile */ PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1,
0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e, PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP2,
/* Lynxpoint Low Power */ PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP3,
0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP4,
PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP5,
PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP6,
PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP7,
PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP8,
PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP1,
PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP2,
PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP3,
PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP4,
PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP5,
PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP6,
0 0
}; };

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@@ -214,9 +214,22 @@ static struct device_operations sata_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */ PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE,
0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */ PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_AHCI,
0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */ PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_1,
PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM,
PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45,
PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_2,
PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE,
PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_AHCI,
PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_1,
PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM,
PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE_P45,
PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_2,
PCI_DEVICE_ID_INTEL_LPT_LP_SATA_AHCI,
PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_1,
PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_PREM,
PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_2,
0 0
}; };

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@@ -228,14 +228,14 @@ static struct device_operations device_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
0x9c60, /* 0:15.0 - SDMA */ PCI_DEVICE_ID_INTEL_LPT_LP_SDMA,
0x9c61, /* 0:15.1 - I2C0 */ PCI_DEVICE_ID_INTEL_LPT_LP_I2C0,
0x9c62, /* 0:15.2 - I2C1 */ PCI_DEVICE_ID_INTEL_LPT_LP_I2C1,
0x9c65, /* 0:15.3 - SPI0 */ PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0,
0x9c66, /* 0:15.4 - SPI1 */ PCI_DEVICE_ID_INTEL_LPT_LP_GSPI1,
0x9c63, /* 0:15.5 - UART0 */ PCI_DEVICE_ID_INTEL_LPT_LP_UART0,
0x9c64, /* 0:15.6 - UART1 */ PCI_DEVICE_ID_INTEL_LPT_LP_UART1,
0x9c35, /* 0:17.0 - SDIO */ PCI_DEVICE_ID_INTEL_LPT_LP_SD,
0 0
}; };

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@@ -80,7 +80,8 @@ static struct device_operations smbus_ops = {
}; };
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
0x8c22, 0x9c22, PCI_DEVICE_ID_INTEL_LPT_H_SMBUS,
PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS,
0 0
}; };

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@@ -169,7 +169,12 @@ static struct device_operations usb_ehci_ops = {
.ops_pci = &lops_pci, .ops_pci = &lops_pci,
}; };
static const unsigned short pci_device_ids[] = { 0x9c26, 0x8c26, 0x8c2d, 0 }; static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_LPT_LP_EHCI,
PCI_DEVICE_ID_INTEL_LPT_H_EHCI_1,
PCI_DEVICE_ID_INTEL_LPT_H_EHCI_2,
0
};
static const struct pci_driver pch_usb_ehci __pci_driver = { static const struct pci_driver pch_usb_ehci __pci_driver = {
.ops = &usb_ehci_ops, .ops = &usb_ehci_ops,

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@@ -342,9 +342,11 @@ static struct device_operations usb_xhci_ops = {
.ops_pci = &pci_dev_ops_pci, .ops_pci = &pci_dev_ops_pci,
}; };
static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */ static const unsigned short pci_device_ids[] = {
0x9c31, /* LynxPoint-LP */ PCI_DEVICE_ID_INTEL_LPT_H_XHCI,
0 }; PCI_DEVICE_ID_INTEL_LPT_LP_XHCI,
0
};
static const struct pci_driver pch_usb_xhci __pci_driver = { static const struct pci_driver pch_usb_xhci __pci_driver = {
.ops = &usb_xhci_ops, .ops = &usb_xhci_ops,

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@@ -8,6 +8,7 @@ tests-y += timestamp-test
tests-y += edid-test tests-y += edid-test
tests-y += cbmem_console-romstage-test tests-y += cbmem_console-romstage-test
tests-y += cbmem_console-ramstage-test tests-y += cbmem_console-ramstage-test
tests-y += list-test
string-test-srcs += tests/lib/string-test.c string-test-srcs += tests/lib/string-test.c
string-test-srcs += src/lib/string.c string-test-srcs += src/lib/string.c
@@ -39,3 +40,7 @@ cbmem_console-romstage-test-srcs += tests/stubs/console.c
cbmem_console-ramstage-test-stage := ramstage cbmem_console-ramstage-test-stage := ramstage
cbmem_console-ramstage-test-srcs += tests/lib/cbmem_console-test.c cbmem_console-ramstage-test-srcs += tests/lib/cbmem_console-test.c
cbmem_console-ramstage-test-srcs += tests/stubs/console.c cbmem_console-ramstage-test-srcs += tests/stubs/console.c
list-test-srcs += tests/lib/list-test.c
list-test-srcs += src/lib/list.c

129
tests/lib/list-test.c Normal file
View File

@@ -0,0 +1,129 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <tests/test.h>
#include <stdlib.h>
#include <string.h>
#include <list.h>
struct test_container {
int value;
struct list_node list_node;
};
void test_list_insert_after(void **state)
{
int i = 0;
struct list_node root = { .prev = NULL, .next = NULL };
struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2));
struct test_container *ptr;
const int values[] = { 5, 10, 13 }; /* Random values */
memset(c1, 0, sizeof(*c1));
memset(c2, 0, sizeof(*c2));
memset(c2, 0, sizeof(*c3));
c1->value = values[0];
c2->value = values[1];
c3->value = values[2];
list_insert_after(&c1->list_node, &root);
list_insert_after(&c2->list_node, &c1->list_node);
list_insert_after(&c3->list_node, &c2->list_node);
list_for_each(ptr, root, list_node) {
assert_int_equal(values[i], ptr->value);
i++;
}
assert_int_equal(3, i);
free(c3);
free(c2);
free(c1);
}
void test_list_insert_before(void **state)
{
int i = 0;
struct list_node root = { .prev = NULL, .next = NULL };
struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2));
struct test_container *ptr;
const int values[] = { 19, 71, 991 }; /* Random values */
memset(c1, 0, sizeof(*c1));
memset(c2, 0, sizeof(*c2));
memset(c2, 0, sizeof(*c3));
c1->value = values[0];
c2->value = values[1];
c3->value = values[2];
list_insert_after(&c3->list_node, &root);
list_insert_before(&c2->list_node, &c3->list_node);
list_insert_before(&c1->list_node, &c2->list_node);
list_for_each(ptr, root, list_node) {
assert_int_equal(values[i], ptr->value);
i++;
}
assert_int_equal(3, i);
free(c3);
free(c2);
free(c1);
}
void test_list_remove(void **state)
{
struct list_node root = { .prev = NULL, .next = NULL };
struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1));
struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2));
struct test_container *ptr;
int len;
list_insert_after(&c1->list_node, &root);
list_insert_after(&c2->list_node, &c1->list_node);
len = 0;
list_for_each(ptr, root, list_node) {
len++;
}
assert_int_equal(2, len);
list_remove(&c1->list_node);
len = 0;
list_for_each(ptr, root, list_node) {
len++;
}
assert_int_equal(1, len);
list_remove(&c2->list_node);
len = 0;
list_for_each(ptr, root, list_node) {
len++;
}
assert_int_equal(0, len);
free(c2);
free(c1);
}
int main(void)
{
const struct CMUnitTest tests[] = {
cmocka_unit_test(test_list_insert_after),
cmocka_unit_test(test_list_insert_before),
cmocka_unit_test(test_list_remove),
};
return cmocka_run_group_tests(tests, NULL, NULL);
}

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