soc/intel/common: add common function to set LT_LOCK_MEMORY
Add a common function for setting LT_LOCK_MEMORY via MSR 0x2E7, which locks most of the chipset BAR registers in accordance to Intel BWG. Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
committed by
Patrick Georgi
parent
af1cbe2278
commit
5ce66da1b5
@@ -23,10 +23,10 @@
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#include <arch/cpu.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/msr.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/pm.h>
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#include <intelblocks/msr.h>
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#include <soc/pci_devs.h>
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#include <stdint.h>
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@@ -320,3 +320,8 @@ void mca_configure(void)
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(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
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}
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}
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void cpu_lt_lock_memory(void *unused)
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{
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msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT);
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}
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@@ -161,4 +161,7 @@ uint32_t cpu_get_max_turbo_ratio(void);
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/* Configure Machine Check Architecture support */
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void mca_configure(void);
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/* Lock chipset memory registers to protect SMM */
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void cpu_lt_lock_memory(void *unused);
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#endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */
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@@ -67,6 +67,8 @@
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#define MSR_POWER_CTL 0x1fc
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#define POWER_CTL_C1E_MASK (1 << 1)
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#define MSR_EVICT_CTL 0x2e0
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#define MSR_LT_CONTROL 0x2e7
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#define LT_CONTROL_LOCK_BIT (0)
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#define MSR_SGX_OWNEREPOCH0 0x300
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#define MSR_SGX_OWNEREPOCH1 0x301
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#define SMM_FEATURE_CONTROL_MSR 0x4e0
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