soc/intel/common: add common function to set LT_LOCK_MEMORY

Add a common function for setting LT_LOCK_MEMORY via MSR 0x2E7, which
locks most of the chipset BAR registers in accordance to Intel BWG.

Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/common/block/cpu/cpulib.c

@@ -23,10 +23,10 @@
 #include <arch/cpu.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/msr.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
-#include <intelblocks/msr.h>
 #include <soc/pci_devs.h>
 #include <stdint.h>
 
@@ -320,3 +320,8 @@ void mca_configure(void)
 			(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
 	}
 }
+
+void cpu_lt_lock_memory(void *unused)
+{
+	msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT);
+}

src/soc/intel/common/block/include/intelblocks/cpulib.h

@@ -161,4 +161,7 @@ uint32_t cpu_get_max_turbo_ratio(void);
 /* Configure Machine Check Architecture support */
 void mca_configure(void);
 
+/* Lock chipset memory registers to protect SMM */
+void cpu_lt_lock_memory(void *unused);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_CPULIB_H */

src/soc/intel/common/block/include/intelblocks/msr.h

@@ -67,6 +67,8 @@
 #define MSR_POWER_CTL			0x1fc
 #define  POWER_CTL_C1E_MASK		(1 << 1)
 #define MSR_EVICT_CTL			0x2e0
+#define MSR_LT_CONTROL			0x2e7
+#define  LT_CONTROL_LOCK_BIT		(0)
 #define MSR_SGX_OWNEREPOCH0		0x300
 #define MSR_SGX_OWNEREPOCH1		0x301
 #define SMM_FEATURE_CONTROL_MSR		0x4e0