soc/amd/stoneyridge: Refactor northbridge resource allocator
The resource allocator was overly complicated due to porting from a multi-node resource allocator. It had some assumptions about the UMA memory and where it would be located. The refactored allocations account for UMA being reserved above 4GiB. TEST=Check CBMEM table has correct RAM regions. Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
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Marc Jones
Martin Roth
parent
932b5bdb6d
commit
5fd1d5ad12
@ -40,35 +40,6 @@
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#include <stdlib.h>
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#include <string.h>
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typedef struct dram_base_mask {
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u32 base; /* [47:27] at [28:8] */
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u32 mask; /* [47:27] at [28:8] and enable at bit 0 */
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} dram_base_mask_t;
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static dram_base_mask_t get_dram_base_mask(void)
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{
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device_t dev = dev_find_slot(0, ADDR_DEVFN);
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dram_base_mask_t d;
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u32 temp;
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/* [39:24] at [31:16] */
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temp = pci_read_config32(dev, 0x44);
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/* mask out DramMask [26:24] too */
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d.mask = ((temp & 0xfff80000) >> (8 + 3));
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/* [47:40] at [7:0] */
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temp = pci_read_config32(dev, 0x144) & 0xff;
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d.mask |= temp << 21;
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temp = pci_read_config32(dev, 0x40);
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d.mask |= (temp & 1); /* enable bit */
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d.base = ((temp & 0xfff80000) >> (8 + 3));
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temp = pci_read_config32(dev, 0x140) & 0xff;
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d.base |= temp << 21;
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return d;
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}
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static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
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u32 io_min, u32 io_max)
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{
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@ -433,109 +404,54 @@ void domain_enable_resources(device_t dev)
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void domain_set_resources(device_t dev)
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{
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unsigned long mmio_basek;
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u32 pci_tolm;
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u32 hole;
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int idx;
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struct bus *link;
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void *tseg_base;
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size_t tseg_size;
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uint64_t uma_base = get_uma_base();
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uint32_t uma_size = get_uma_size();
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uint32_t mem_useable = (uintptr_t)cbmem_top();
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msr_t tom = rdmsr(TOP_MEM);
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msr_t high_tom = rdmsr(TOP_MEM2);
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uint64_t high_mem_useable;
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int idx = 0x10;
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pci_tolm = 0xffffffffUL;
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for (link = dev->link_list ; link ; link = link->next)
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pci_tolm = find_pci_tolm(link);
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/* 0x0 -> 0x9ffff */
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ram_resource(dev, idx++, 0, 0xa0000 / KiB);
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/* Start with alignment supportable in variable MTRR */
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mmio_basek = ALIGN_DOWN(pci_tolm, 4 * KiB) / KiB;
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/* 0xa0000 -> 0xbffff: legacy VGA */
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mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
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/* 0xc0000 -> 0xfffff: Option ROM */
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reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
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/*
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* AGESA may have programmed the memory hole and rounded down to a
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* 128MB boundary. If we find it's valid, adjust mmio_basek downward
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* to the hole bottom. D18F1xF0[DramHoleBase] is granular to 16MB.
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* 0x100000 (1MiB) -> low top useable RAM
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* cbmem_top() accounts for low UMA and TSEG if they are used.
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*/
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hole = pci_read_config32(dev_find_slot(0, ADDR_DEVFN), D18F1_DRAM_HOLE);
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if (hole & DRAM_HOLE_VALID)
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mmio_basek = min(mmio_basek, ALIGN_DOWN(hole, 16 * MiB) / KiB);
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ram_resource(dev, idx++, (1 * MiB) / KiB,
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(mem_useable - (1 * MiB)) / KiB);
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idx = 0x10;
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dram_base_mask_t d;
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resource_t basek, limitk, sizek; /* 4 1T */
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/* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */
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reserved_ram_resource(dev, idx++, mem_useable / KiB,
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(tom.lo - mem_useable) / KiB);
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d = get_dram_base_mask();
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/* If there is memory above 4GiB */
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if (high_tom.hi) {
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/* 4GiB -> high top useable */
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if (uma_base >= (4ull * GiB))
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high_mem_useable = uma_base;
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else
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high_mem_useable = ((uint64_t)high_tom.lo |
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((uint64_t)high_tom.hi << 32));
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if ((d.mask & 1)) { /* if enabled... */
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/* could overflow, we may lose 6 bit here */
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basek = ((resource_t)(d.base & 0x1fffff00)) << 9;
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limitk = ((resource_t)(((d.mask & ~1) + 0x000ff)
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& 0x1fffff00)) << 9;
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sizek = limitk - basek;
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/* see if we need a hole from 0xa0000 to 0xbffff */
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if ((basek < ((8 * 64) + (8 * 16))) && (sizek > ((8 * 64) +
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(16 * 16)))) {
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ram_resource(dev, idx, basek,
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((8 * 64) + (8 * 16)) - basek);
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idx += 0x10;
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basek = (8 * 64) + (16 * 16);
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sizek = limitk - ((8 * 64) + (16 * 16));
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ram_resource(dev, idx++, (4ull * GiB) / KiB,
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((high_mem_useable - (4ull * GiB)) / KiB));
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/* High top useable RAM -> high top RAM */
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if (uma_base >= (4ull * GiB)) {
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reserved_ram_resource(dev, idx++, uma_base / KiB,
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uma_size / KiB);
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}
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/* split the region to accommodate pci memory space */
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if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
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if (basek <= mmio_basek) {
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unsigned int pre_sizek;
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pre_sizek = mmio_basek - basek;
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if (pre_sizek > 0) {
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ram_resource(dev, idx, basek,
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pre_sizek);
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idx += 0x10;
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sizek -= pre_sizek;
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}
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basek = mmio_basek;
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}
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if ((basek + sizek) <= 4 * 1024 * 1024) {
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sizek = 0;
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} else {
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uint64_t topmem2 = bsp_topmem2();
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basek = 4 * 1024 * 1024;
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sizek = topmem2 / 1024 - basek;
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}
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}
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ram_resource(dev, idx, basek, sizek);
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printk(BIOS_DEBUG, "node 0: mmio_basek=%08lx, basek=%08llx,"
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" limitk=%08llx\n", mmio_basek, basek, limitk);
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}
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/* UMA is not set up yet, but infer the base & size to make cacheable */
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uint32_t uma_base = restore_top_of_low_cacheable();
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if (uma_base != bsp_topmem()) {
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uint32_t uma_size = bsp_topmem() - uma_base;
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printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n",
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__func__, uma_size, uma_base);
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reserved_ram_resource(dev, 7, uma_base / KiB, uma_size / KiB);
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}
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for (link = dev->link_list ; link ; link = link->next)
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if (link->children)
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assign_resources(link);
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/*
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* Reserve everything between A segment and 1MB:
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*
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* 0xa0000 - 0xbffff: legacy VGA
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* 0xc0000 - 0xfffff: RAM
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*/
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mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB);
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reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB);
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/* Reserve TSEG */
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smm_region_info(&tseg_base, &tseg_size);
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idx += 0x10;
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reserved_ram_resource(dev, idx, (unsigned long)tseg_base/KiB,
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tseg_size/KiB);
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assign_resources(dev->link_list);
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}
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/*********************************************************************
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