soc/ibm/power9/*: add file structure for SOC

Boot device is stubbed to be able to build boards without errors.

Change-Id: Ie74b1e34f9aebe151d0fdb0e95c003510fd864c3
Signed-off-by: Igor Bagnucki <bagnucki02@gmail.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

src/soc/ibm/power9/Kconfig

@@ -0,0 +1,14 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_IBM_POWER9
+	bool
+	select ARCH_BOOTBLOCK_PPC64
+	select ARCH_VERSTAGE_PPC64
+	select ARCH_ROMSTAGE_PPC64
+	select ARCH_RAMSTAGE_PPC64
+	help
+	  This SoC is the minimal template working on POWER9 Talos II platform.
+
+if SOC_IBM_POWER9
+	# nothing here yet
+endif

src/soc/ibm/power9/Makefile.mk

@@ -0,0 +1,17 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_SOC_IBM_POWER9),y)
+
+bootblock-y += bootblock.c
+bootblock-y += rom_media.c
+
+romstage-y += cbmem.c
+romstage-y += rom_media.c
+romstage-y += romstage.c
+
+ramstage-y += cbmem.c
+ramstage-y += chip.c
+ramstage-y += rom_media.c
+ramstage-y += timer.c
+
+endif

src/soc/ibm/power9/bootblock.c

@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+
+void bootblock_soc_early_init(void)
+{
+}

src/soc/ibm/power9/cbmem.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+
+uintptr_t cbmem_top_chipset(void)
+{
+	/*
+	 * Smallest reported to be working (but not officially supported) DIMM is
+	 * 4GB. This means that we always have at least as much available. Last
+	 * 256MB are reserved for hostboot/coreboot (OCC and HOMER images).
+	 *
+	 * TODO: implement this properly after RAM is detected.
+	 */
+	return 4ull * GiB - 256 * MiB;
+}

src/soc/ibm/power9/chip.c

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+#include <device/device.h>
+
+static void enable_soc_dev(struct device *dev)
+{
+	ram_range(dev, 0, 0, cbmem_top_chipset());
+	/* This is for OCC and HOMER images */
+	reserved_ram_range(dev, 1, cbmem_top_chipset(), 256 * MiB);
+}
+
+struct chip_operations soc_ibm_power9_ops = {
+	.name = "POWER9",
+	.enable_dev = enable_soc_dev,
+};

src/soc/ibm/power9/rom_media.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot_device.h>
+
+const struct region_device *boot_device_ro(void)
+{
+	return NULL;
+}

src/soc/ibm/power9/romstage.c

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <program_loading.h>
+
+void main(void)
+{
+	console_init();
+	cbmem_initialize_empty();
+	run_ramstage();
+}

src/soc/ibm/power9/timer.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <delay.h>
+
+void init_timer(void)
+{
+	/* No need to do anything here as long as udelay() is implemented via monolitic timer */
+}