remove trailing whitespace

Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/cpu/amd/model_10xxx/defaults.h

@@ -91,7 +91,7 @@ static const struct {
 
 	{ BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
 	  0x00000000, 1 << (35-32),
-	  0x00000000, 1 << (35-32) },	/* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() )  */  
+	  0x00000000, 1 << (35-32) },	/* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() )  */
 
 	{ OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
 	  0x00000004, 0x00000000,

src/cpu/amd/model_10xxx/fidvid.c

@@ -17,84 +17,84 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 /*
- * This file initializes the CPU cores for voltage and frequency settings 
+ * This file initializes the CPU cores for voltage and frequency settings
  * in the different power states.
  */
 /*
 
 checklist (functions are in this file if no source file named)
-Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 
+Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
 
 2.4.2.6 Requirements for p-states
 
 1.- F3x[84:80] According to table 100 : prep_fid_change
 
-2.- COF/VID : 
-     2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply 
-               fixPsNbVidBeforeWR(...) 
+2.- COF/VID :
+     2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply
+               fixPsNbVidBeforeWR(...)
      2.4.2.9.1 Step 8 enable_fid_change
-               We do this for all nodes, I don't understand BKDG 100% on 
-               whether this is or isn't meant by "on the local 
+               We do this for all nodes, I don't understand BKDG 100% on
+               whether this is or isn't meant by "on the local
                processor". Must be OK.
      2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ?
      2.4.2.9.1 Steps 11-12 init_fidvid_stage2
-     2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect, 
-               needs specific circuitry. 
+     2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect,
+               needs specific circuitry.
 
 3.-  2.4.2.7 dualPlaneOnly(dev)
 
 4.-  2.4.2.8 applyBoostFIDOffset(dev)
 
-5.-  enableNbPState1(dev) 
+5.-  enableNbPState1(dev)
 
-6.- 2.4.1.7 
+6.- 2.4.1.7
     a) UpdateSinglePlaneNbVid()
     b) setVSRamp(), called from  prep_fid_change
     c) prep_fid_change
-    d) improperly, for lack of voltage regulator details?, 
-        F3xA0[PsiVidEn] in defaults.h 
+    d) improperly, for lack of voltage regulator details?,
+        F3xA0[PsiVidEn] in defaults.h
         F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change)
 
-7.- TODO (Core Performance Boost is only available in revision E cpus, and we 
-          don't seem to support those yet, at least they don't have any 
+7.- TODO (Core Performance Boost is only available in revision E cpus, and we
+          don't seem to support those yet, at least they don't have any
           constant in amddefs.h )
 
-8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required 
-    by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required 
-    if the warm reset is issued by coreboot to update NbFid. So it is required 
-    or not ? How can I tell who issued warm reset ? 
-    Coreboot transitions to P0 instead, which is not recommended, and does 
+8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required
+    by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
+    if the warm reset is issued by coreboot to update NbFid. So it is required
+    or not ? How can I tell who issued warm reset ?
+    Coreboot transitions to P0 instead, which is not recommended, and does
     not follow 2.4.2.15.2 to do so.
 
-9.- TODO Requires information on current delivery capability 
-    (depends on mainboard and maybe power supply ?). One might use a config 
+9.- TODO Requires information on current delivery capability
+    (depends on mainboard and maybe power supply ?). One might use a config
     option with the maximum number of Ampers that the board can deliver to CPU.
 
 10.- [Multiprocessor] TODO 2.4.2.12
-     [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2, 
-     but not sure this is what is meant by "Determine the valid set of 
-     P-states based on enabled P-states indicated 
+     [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2,
+     but not sure this is what is meant by "Determine the valid set of
+     P-states based on enabled P-states indicated
      in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10
 
 11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway)
 
-12.- generate ACPI for p-states. FIXME 
+12.- generate ACPI for p-states. FIXME
      Needs more assesment. There's some kind of fixed support that
      does not seem to depend on CPU revision or actual MSRC001_00[68:64]
-     as BKDG apparently requires. 
+     as BKDG apparently requires.
      http://www.coreboot.org/ACPI#CPU_Power_Management
      At least for Tilapia board:
      src/mainboard/<vendor>/<model>/acpi_tables.c  write_acpi_tables(...) calls
-      acpi_add_ssdt_pstates(...) 
+      acpi_add_ssdt_pstates(...)
      in /src/northbridge/amd/amdfam10/amdfam10_acpi.c
      which apparently copies them from static info in
-     src/mainboard/<vendor>/<model>/acpi/cpstate.asl 
-     
+     src/mainboard/<vendor>/<model>/acpi/cpstate.asl
+
 "must also be completed"
 
 a.-  PllLockTime set in ruleset in defaults.h
-     BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between 
-     any two enabled P-states", but since it does not say "only if" 
+     BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between
+     any two enabled P-states", but since it does not say "only if"
      I guess it is safe to do it always.
 
 b.-  prep_fid_change(...)

src/cpu/amd/model_fxx/model_fxx_init.c

@@ -265,7 +265,7 @@ static void init_ecc_memory(unsigned node_id)
 
 	/* See if we scrubbing should be enabled */
 	enable_scrubbing = 1;
-	if( get_option(&enable_scrubbing, "hw_scrubber") < 0 ) 
+	if( get_option(&enable_scrubbing, "hw_scrubber") < 0 )
 	{
 		enable_scrubbing = CONFIG_HW_SCRUBBER;
 	}
@@ -443,7 +443,7 @@ static inline void k8_errata(void)
 #endif
 	{
 		msr = rdmsr(NB_CFG_MSR);
-		
+
 #if CONFIG_K8_REV_F_SUPPORT == 0
 		if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
 			/* D0 later don't need it */
@@ -461,11 +461,11 @@ static inline void k8_errata(void)
 		 */
 		msr.lo |= 1 << 3;
 		/* Erratum 169 */
-		/* This supersedes erratum 131; 131 should not be applied with 169 
+		/* This supersedes erratum 131; 131 should not be applied with 169
 		 * We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/
 		 */
 		msr.hi |= 1;
-		
+
 		wrmsr(NB_CFG_MSR, msr);
 	}
 	/* Erratum 122 */

src/cpu/amd/model_gx2/cpubug.c

@@ -280,7 +280,7 @@ static void bug118339(void)
 
 	/* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
 	 * As per Todd Roberts in PBz1094 and PBz1095
-	 * Moved from CPUREG to CPUBUG per Tom Sylla 
+	 * Moved from CPUREG to CPUBUG per Tom Sylla
 	 */
 	msrnum =  0x04C000042;		/*  GLCP SETMCTL Register */
 	msr = rdmsr(msrnum);

src/cpu/amd/model_lx/cpureginit.c

@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
  * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
@@ -83,7 +83,7 @@ static const struct delay_controls {
  * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger)
  * is hooked up, then just don't do anything. This code was written by a master
  * of the Dark Arts at AMD and should not be modified in any way.
- * 
+ *
  * [1] (http://www.thefreedictionary.com/juju)
  *
  * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).

src/cpu/amd/model_lx/msrinit.c

@@ -45,7 +45,7 @@ static const msrinit_t msr_table[] =
 	 * of this extended memory will be to host the coreboot_ram stage at RAMBASE,
 	 * currently 1Mb.
 	 * These registers will be set to their correct value by the Northbridge init code.
-	 * 
+	 *
 	 * WARNING: if coreboot_ram could not be loaded, these registers are probably
 	 * incorrectly set here. You may comment the following two lines and set RAMBASE
 	 * to 0x4000 to revert to the previous behavior for LX-boards.