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soc/amd/cezanne: fix i2c compiler errors on non-x86

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if ENV_X86 is not true we had several compile errors in i2c code. Fix
them before we add code for psp_verstage which is non-x86.

BUG=b:182477057
BRANCH=none
TEST=build

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I0796671dd34ab2d0f123c904a88c57cdad116a57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kangheui Won
2021-04-15 17:34:09 +10:00
committed by Felix Held
parent f299632831
commit 62047e582b
3 changed files with 8 additions and 6 deletions
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3
src/soc/amd/cezanne/i2c.c
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@@ -2,6 +2,7 @@
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <amdblocks/i2c.h> #include <amdblocks/i2c.h>
#include <console/console.h>
#include <soc/i2c.h> #include <soc/i2c.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
#include "chip.h" #include "chip.h"
@@ -14,7 +15,7 @@ static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
{ I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" } { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" }
}; };
#else #else
static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_CNT] = { static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
{ I2C_MASTER_MODE, 0, "" }, { I2C_MASTER_MODE, 0, "" },
{ I2C_MASTER_MODE, 0, "" }, { I2C_MASTER_MODE, 0, "" },
{ I2C_MASTER_MODE, 0, "" }, { I2C_MASTER_MODE, 0, "" },

1
src/soc/amd/cezanne/include/soc/i2c.h
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@@ -22,5 +22,6 @@
#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx
#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
void i2c_set_bar(unsigned int bus, uintptr_t bar);
#endif /* AMD_CEZANNE_I2C_H */ #endif /* AMD_CEZANNE_I2C_H */

10
src/soc/amd/cezanne/include/soc/iomap.h
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@@ -3,6 +3,11 @@
#ifndef AMD_CEZANNE_IOMAP_H #ifndef AMD_CEZANNE_IOMAP_H
#define AMD_CEZANNE_IOMAP_H #define AMD_CEZANNE_IOMAP_H
#define I2C_MASTER_DEV_COUNT 4
#define I2C_MASTER_START_INDEX 0
#define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */
#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
#if ENV_X86 #if ENV_X86
/* MMIO Ranges */ /* MMIO Ranges */
@@ -16,11 +21,6 @@
/* FCH AL2AHB Registers */ /* FCH AL2AHB Registers */
#define ALINK_AHB_ADDRESS 0xfedc0000 #define ALINK_AHB_ADDRESS 0xfedc0000
#define I2C_MASTER_DEV_COUNT 4
#define I2C_MASTER_START_INDEX 0
#define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */
#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
#define APU_I2C0_BASE 0xfedc2000 #define APU_I2C0_BASE 0xfedc2000
#define APU_I2C1_BASE 0xfedc3000 #define APU_I2C1_BASE 0xfedc3000
#define APU_I2C2_BASE 0xfedc4000 #define APU_I2C2_BASE 0xfedc4000