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mb/system76/rpl: oryp11: Add USB and PCIe RP configs

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Change-Id: Ibe15461b58a5d133456779e7e28c8bd1db7ee320
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2023-02-09 09:12:19 -07:00
committed by Jeremy Soller
parent 4a9e7c2bd0
commit 626b3c47bf
1 changed files with 79 additions and 0 deletions
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79
src/mainboard/system76/rpl/variants/oryp11/overridetree.cb
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@@ -1,5 +1,84 @@
chip soc/intel/alderlake
device domain 0 on
subsystemid 0x1558 0xd502 inherit
device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC2 (USB 3.1 Gen2 + DP 1.4 HBR3)
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # AJ_USB1 (USB 3.2 Gen2)
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # AJ_USB2 (USB 3.2 Gen2 + charger)
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Per-KB
register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TBT USB2.0
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPEC2 (USB 3.1 Gen2 + DP 1.4 HBR3)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # AJ_USB1 (USB 3.2 Gen2)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # AJ_USB2 (USB 3.2 Gen2 + charger)
end
device ref pcie5_1 off
# CPU PCIe RP#2 x8, Clock 14 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 14,
.clk_req = 14,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp3 on
# PCH RP#3 x1, Clock 13 (GLAN)
register "pch_pcie_rp[PCH_RP(3)]" = "{
.clk_src = 13,
.clk_req = 13,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp5 on
# PCH RP#5 x1, Clock 12 (CARD)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 12,
.clk_req = 12,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp8 on
# PCH RP#8 x1, Clock 11 (WLAN)
register "pch_pcie_rp[PCH_RP(8)]" = "{
.clk_src = 11,
.clk_req = 11,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp13 on
# PCH RP#13 x4, Clock 10 (SSD1)
register "pch_pcie_rp[PCH_RP(13)]" = "{
.clk_src = 10,
.clk_req = 10,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp21 on
# PCH RP#21 x4, Clock 5 (SSD2)
register "pch_pcie_rp[PCH_RP(21)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp25 on
# PCH RP#25 x4, Clock 15 (TBT)
register "pch_pcie_rp[PCH_RP(21)]" = "{
.clk_src = 15,
.clk_req = 15,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
end
end