mainboard/winnet/g170: Copy from mainboard/bcom/winnetp680
G170 is a board manufactured by WinNET, used in thin clients including HP Neoware CA19 and IGEL 2110. Copied from mainboard/bcom/winnetp680 which seems to be a similar board with an extra PCI slot. The p680 should probably be moved to winnet/ too, since the board is an OEM WinNET board, with BCom being just a machine that happens to it. Change-Id: I90b89ee634d90cfba2e56cca5b76cfd2bd7a8d0b Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Lubomir Rintel
Martin Roth
parent
925337a633
commit
64b53d66df
25
src/mainboard/winnet/g170/Kconfig
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25
src/mainboard/winnet/g170/Kconfig
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@ -0,0 +1,25 @@
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if BOARD_BCOM_WINNETP680
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_VIA_C7
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select NORTHBRIDGE_VIA_CN700
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select SOUTHBRIDGE_VIA_VT8237R
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select SUPERIO_WINBOND_W83697HF
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select HAVE_PIRQ_TABLE
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select HAVE_OPTION_TABLE
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select BOARD_ROMSIZE_KB_512
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config MAINBOARD_DIR
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string
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default bcom/winnetp680
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config MAINBOARD_PART_NUMBER
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string
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default "WinNET P680"
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config IRQ_SLOT_COUNT
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int
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default 10
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endif # BOARD_BCOM_WINNETP680
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2
src/mainboard/winnet/g170/Kconfig.name
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2
src/mainboard/winnet/g170/Kconfig.name
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config BOARD_BCOM_WINNETP680
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bool "WinNET P680"
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1
src/mainboard/winnet/g170/board_info.txt
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1
src/mainboard/winnet/g170/board_info.txt
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Category: settop
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36
src/mainboard/winnet/g170/cmos.layout
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36
src/mainboard/winnet/g170/cmos.layout
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entries
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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456 1 e 1 ECC_memory
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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checksums
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checksum 392 1007 1008
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64
src/mainboard/winnet/g170/devicetree.cb
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64
src/mainboard/winnet/g170/devicetree.cb
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@ -0,0 +1,64 @@
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chip northbridge/via/cn700 # Northbridge
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device domain 0 on # PCI domain
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device pci 0.0 on end # AGP Bridge
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device pci 0.1 on end # Error Reporting
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device pci 0.2 on end # Host Bus Control
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device pci 0.3 on end # Memory Controller
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device pci 0.4 on end # Power Management
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device pci 0.7 on end # V-Link Controller
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device pci 1.0 on end # PCI Bridge
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chip southbridge/via/vt8237r # Southbridge
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# Enable both IDE channels.
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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# Both cables are 40pin.
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register "ide0_80pin_cable" = "0"
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register "ide1_80pin_cable" = "0"
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register "fn_ctrl_lo" = "0x80"
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register "fn_ctrl_hi" = "0x1d"
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device pci f.0 on end # IDE
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device pci 10.0 on end # UHCI
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device pci 10.1 on end # UHCI
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device pci 10.2 on end # UHCI
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device pci 10.3 on end # UHCI
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device pci 10.4 on end # EHCI
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device pci 11.0 on # Southbridge LPC
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chip superio/winbond/w83697hf # Super I/O
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.6 off end # Consumer IR
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device pnp 2e.7 off end # Game port, GPIO 1
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device pnp 2e.8 off end # MIDI port, GPIO 5
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device pnp 2e.9 off end # GPIO 2-4
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HWM
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io 0x60 = 0x290
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end
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end
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end
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device pci 11.5 on end # AC'97 audio
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device pci 12.0 on end # Ethernet
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end
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end
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device cpu_cluster 0 on # APIC cluster
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chip cpu/via/c7 # VIA C7
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device lapic 0 on end # APIC
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end
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end
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end
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50
src/mainboard/winnet/g170/irq_tables.c
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50
src/mainboard/winnet/g170/irq_tables.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 VIA Technologies, Inc.
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* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/pirq_routing.h>
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static const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE,
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PIRQ_VERSION,
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32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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(0x11 << 3) | 0x0, /* Interrupt router device */
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0x828, /* IRQs devoted exclusively to PCI usage */
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0x1106, /* Vendor */
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0x596, /* Device */
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0, /* Miniport data */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x3e, /* Checksum */
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{
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
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{0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
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{0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
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{0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
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{0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
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{0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
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{0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
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{0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
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{0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
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{0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr, &intel_irq_routing_table);
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}
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95
src/mainboard/winnet/g170/romstage.c
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95
src/mainboard/winnet/g170/romstage.c
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@ -0,0 +1,95 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 VIA Technologies, Inc.
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* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <console/console.h>
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#include <northbridge/via/cn700/raminit.h>
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#include <cpu/x86/bist.h>
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#include <cpu/amd/car.h>
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#include <delay.h>
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#include <lib.h>
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#include <spd.h>
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#include <southbridge/via/vt8237r/vt8237r.h>
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/w83697hf/w83697hf.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
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int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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static void enable_mainboard_devices(void)
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{
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pci_devfn_t dev;
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
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if (dev == PCI_DEV_INVALID)
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die("Southbridge not found!!!\n");
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/* bit = 0 means enable function (per CX700 datasheet)
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* 5 16.1 USB 2
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* 4 16.0 USB 1
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* 3 15.0 SATA and PATA
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* 2 16.2 USB 3
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* 1 16.4 USB EHCI
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*/
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pci_write_config8(dev, 0x50, 0x80);
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/* bit = 1 means enable internal function (per CX700 datasheet)
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* 3 Internal RTC
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* 2 Internal PS2 Mouse
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* 1 Internal KBC Configuration
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* 0 Internal Keyboard Controller
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*/
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pci_write_config8(dev, 0x51, 0x1d);
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}
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static const struct mem_controller ctrl = {
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.d0f0 = 0x0000,
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.d0f2 = 0x2000,
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.d0f3 = 0x3000,
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.d0f4 = 0x4000,
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.d0f7 = 0x7000,
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.d1f0 = 0x8000,
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.channel0 = { DIMM0 },
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};
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void main(unsigned long bist)
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{
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/* Enable multifunction for northbridge. */
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pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
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w83697hf_set_clksel_48(SERIAL_DEV);
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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enable_smbus();
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smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0));
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/* Halt if there was a built-in self test failure. */
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report_bist_failure(bist);
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enable_mainboard_devices();
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ddr_ram_setup(&ctrl);
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}
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