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cml-u: enable s0ix and c6dram

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This commit is contained in:
Jeremy Soller
2020-06-04 08:40:48 -06:00
parent 27753e2b4f
commit 64faf29f6b
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/system76/cml-u/devicetree.cb
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@@ -13,8 +13,8 @@ chip soc/intel/cannonlake
register "SendVrMbxCmd" = "2"
# ACPI (soc/intel/cannonlake/acpi.c)
# Disable s0ix
register "s0ix_enable" = "0"
# Enable s0ix
register "s0ix_enable" = "1"
# PM Timer Enabled
register "PmTimerDisabled" = "0"
@@ -37,7 +37,7 @@ chip soc/intel/cannonlake
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_Enabled"
#register "enable_c6dram" = "1"
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
# Serial I/O
@@ -227,7 +227,7 @@ chip soc/intel/cannonlake
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end # I2C #0
end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3