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oryp11: dGPU port and TP GPIO

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Change-Id: Ie3f9edbf5cb9fcaba3c50e949afb55f990cd846d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2023-02-10 13:43:56 -07:00
parent dbf7480795
commit 654a08acd4
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/system76/rpl/variants/oryp11/gpio.c
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@@ -122,7 +122,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_E4, NONE), PAD_NC(GPP_E4, NONE),
PAD_NC(GPP_E5, NONE), PAD_NC(GPP_E5, NONE),
PAD_NC(GPP_E6, NONE), PAD_NC(GPP_E6, NONE),
_PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000), // TP_ATTN# PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#

2
src/mainboard/system76/rpl/variants/oryp11/overridetree.cb
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@@ -18,7 +18,7 @@ chip soc/intel/alderlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # AJ_USB2 (USB 3.2 Gen2 + charger) register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # AJ_USB2 (USB 3.2 Gen2 + charger)
end end
device ref pcie5_1 off device ref pcie5_0 on
# CPU PCIe RP#2 x8, Clock 14 (DGPU) # CPU PCIe RP#2 x8, Clock 14 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{ register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 14, .clk_src = 14,