AGESA,binaryPI: Move PORT80 selection to C bootblock

Because the function is implemented in C, post_code() calls
from cache_as_ram.S and other early assembly entry files may
not currently work for cold boots. Assembly implementation
needs to follow one day.

This effectively removes PORT80 routing from boards with
ROMCC_BOOTBLOCK.

Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>

src/mainboard/amd/bettong/Kconfig

@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_PI_00660F01
 	select NORTHBRIDGE_AMD_PI_00660F01
 	select SOUTHBRIDGE_AMD_PI_KERN
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/bettong/romstage.c

@@ -29,8 +29,6 @@ static void romstage_main_template(void)
 {
 	u32 val;
 
-	hudson_lpc_port80();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 

src/mainboard/amd/db-ft3b-lc/Kconfig

@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/db-ft3b-lc/romstage.c

@@ -37,8 +37,6 @@ static void romstage_main_template(void)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	hudson_lpc_port80();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 

src/mainboard/amd/lamar/Kconfig

@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_PI_00630F01
 	select NORTHBRIDGE_AMD_PI_00630F01
 	select SOUTHBRIDGE_AMD_PI_BOLTON
+	select DEFAULT_POST_ON_LPC
 	select SUPERIO_FINTEK_F81216H
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE

src/mainboard/amd/lamar/romstage.c

@@ -48,8 +48,6 @@ static void romstage_main_template(void)
 	*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
 	*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
 
-	hudson_lpc_port80();
-
 	if (!cpu_init_detectedx) {
 		post_code(0x30);
 		f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777);

src/mainboard/amd/olivehill/Kconfig

@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY16_KB
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/olivehill/romstage.c

@@ -41,8 +41,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);
 
-	hudson_lpc_port80();
-
 	/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
 	for (i = 0; i < 200000; i++)
 		val = inb(0xcd6);

src/mainboard/amd/olivehillplus/Kconfig

@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/olivehillplus/romstage.c

@@ -37,8 +37,6 @@ static void romstage_main_template(void)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	hudson_lpc_port80();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 

src/mainboard/amd/parmer/Kconfig

@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY15_TN
 	select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
 	select SOUTHBRIDGE_AMD_AGESA_HUDSON
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/parmer/romstage.c

@@ -19,8 +19,6 @@
 
 void board_BeforeAgesa(struct sysinfo *cb)
 {
-	hudson_lpc_port80();
-
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 
 	/* For serial port option, plug-in card on LPC. */

src/mainboard/amd/thatcher/Kconfig

@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY15_TN
 	select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
 	select SOUTHBRIDGE_AMD_AGESA_HUDSON
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/thatcher/romstage.c

@@ -31,7 +31,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 
 	/* Set LPC decode enables. */
 	dev = PCI_DEV(0, 0x14, 3);
-	hudson_lpc_port80();
 
 	byte = pci_read_config8(dev, 0x48);
 	byte |= 3;		/* 2e, 2f */