AGESA,binaryPI: Move PORT80 selection to C bootblock

Because the function is implemented in C, post_code() calls
from cache_as_ram.S and other early assembly entry files may
not currently work for cold boots. Assembly implementation
needs to follow one day.

This effectively removes PORT80 routing from boards with
ROMCC_BOOTBLOCK.

Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>

src/console/Kconfig

@@ -417,6 +417,7 @@ config POST_DEVICE
 choice
 	prompt "Device to send POST codes to"
 	depends on POST_DEVICE
+	default POST_DEVICE_LPC if DEFAULT_POST_ON_LPC
 	default POST_DEVICE_NONE
 
 config POST_DEVICE_NONE
@@ -429,6 +430,10 @@ config POST_DEVICE_PCI_PCIE
 	depends on PCI
 endchoice
 
+config DEFAULT_POST_ON_LPC
+	bool
+	default n
+
 config POST_IO
 	bool "Send POST codes to an IO port"
 	depends on PC80_SYSTEM && !NO_POST

src/mainboard/amd/bettong/Kconfig

@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_PI_00660F01
 	select NORTHBRIDGE_AMD_PI_00660F01
 	select SOUTHBRIDGE_AMD_PI_KERN
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/bettong/romstage.c

@@ -29,8 +29,6 @@ static void romstage_main_template(void)
 {
 	u32 val;
 
-	hudson_lpc_port80();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 

src/mainboard/amd/db-ft3b-lc/Kconfig

@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/db-ft3b-lc/romstage.c

@@ -37,8 +37,6 @@ static void romstage_main_template(void)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	hudson_lpc_port80();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 

src/mainboard/amd/lamar/Kconfig

@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_PI_00630F01
 	select NORTHBRIDGE_AMD_PI_00630F01
 	select SOUTHBRIDGE_AMD_PI_BOLTON
+	select DEFAULT_POST_ON_LPC
 	select SUPERIO_FINTEK_F81216H
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE

src/mainboard/amd/lamar/romstage.c

@@ -48,8 +48,6 @@ static void romstage_main_template(void)
 	*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
 	*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
 
-	hudson_lpc_port80();
-
 	if (!cpu_init_detectedx) {
 		post_code(0x30);
 		f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777);

src/mainboard/amd/olivehill/Kconfig

@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY16_KB
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/olivehill/romstage.c

@@ -41,8 +41,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);
 
-	hudson_lpc_port80();
-
 	/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
 	for (i = 0; i < 200000; i++)
 		val = inb(0xcd6);

src/mainboard/amd/olivehillplus/Kconfig

@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/olivehillplus/romstage.c

@@ -37,8 +37,6 @@ static void romstage_main_template(void)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	hudson_lpc_port80();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 

src/mainboard/amd/parmer/Kconfig

@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY15_TN
 	select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
 	select SOUTHBRIDGE_AMD_AGESA_HUDSON
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/parmer/romstage.c

@@ -19,8 +19,6 @@
 
 void board_BeforeAgesa(struct sysinfo *cb)
 {
-	hudson_lpc_port80();
-
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 
 	/* For serial port option, plug-in card on LPC. */

src/mainboard/amd/thatcher/Kconfig

@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY15_TN
 	select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
 	select SOUTHBRIDGE_AMD_AGESA_HUDSON
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/amd/thatcher/romstage.c

@@ -31,7 +31,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 
 	/* Set LPC decode enables. */
 	dev = PCI_DEV(0, 0x14, 3);
-	hudson_lpc_port80();
 
 	byte = pci_read_config8(dev, 0x48);
 	byte |= 3;		/* 2e, 2f */

src/mainboard/asrock/imb-a180/Kconfig

@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY16_KB
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+	select DEFAULT_POST_ON_LPC
 	select SUPERIO_WINBOND_W83627UHG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE

src/mainboard/asrock/imb-a180/romstage.c

@@ -35,8 +35,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);
 
-	hudson_lpc_port80();
-
 	/* Enable the AcpiMmio space */
 	outb(0x24, 0xcd6);
 	outb(0x1, 0xcd7);

src/mainboard/asus/am1i-a/Kconfig

@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+	select DEFAULT_POST_ON_LPC
 	select SUPERIO_ITE_IT8623E
 	select MAINBOARD_HAS_LPC_TPM
 

src/mainboard/asus/am1i-a/romstage.c

@@ -142,8 +142,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev2, 0x44, 0xff03ffd5);
 
-	hudson_lpc_port80();
-
 	/* Enable the AcpiMmio space */
 	outb(0x24, 0xcd6);
 	outb(0x1, 0xcd7);

src/mainboard/asus/f2a85-m/romstage.c

@@ -68,11 +68,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	u8 byte;
 	pci_devfn_t dev;
 
-	if (CONFIG(POST_DEVICE_PCI_PCIE))
-		hudson_pci_port80();
-	else if (CONFIG(POST_DEVICE_LPC))
-		hudson_lpc_port80();
-
 	/* enable SIO LPC decode */
 	dev = PCI_DEV(0, 0x14, 3);
 	byte = pci_read_config8(dev, 0x48);

src/mainboard/bap/ode_e20XX/Kconfig

@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY16_KB
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/bap/ode_e20XX/romstage.c

@@ -36,7 +36,5 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);
 
-	hudson_lpc_port80();
-
 	fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
 }

src/mainboard/bap/ode_e21XX/Kconfig

@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/bap/ode_e21XX/romstage.c

@@ -41,8 +41,6 @@ static void romstage_main_template(void)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	hudson_lpc_port80();
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 		fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);

src/mainboard/biostar/a68n_5200/romstage.c

@@ -58,12 +58,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);
 
-	if (CONFIG(POST_DEVICE_PCI_PCIE))
-		hudson_pci_port80();
-
-	if (CONFIG(POST_DEVICE_LPC))
-		hudson_lpc_port80();
-
 	/* enable SIO LPC decode */
 	byte = pci_read_config8(dev, 0x48);
 	byte |= 3;	/* 2e, 2f */

src/mainboard/biostar/am1ml/Kconfig

@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+	select DEFAULT_POST_ON_LPC
 	select SUPERIO_ITE_IT8728F
 
 config MAINBOARD_DIR

src/mainboard/biostar/am1ml/romstage.c

@@ -89,8 +89,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev2, 0x44, 0xff03ffd5);
 
-	hudson_lpc_port80();
-
 	/* Enable the AcpiMmio space */
 	outb(0x24, 0xcd6);
 	outb(0x1, 0xcd7);

src/mainboard/gizmosphere/gizmo2/Kconfig

@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY16_KB
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+	select DEFAULT_POST_ON_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/gizmosphere/gizmo2/romstage.c

@@ -24,8 +24,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);
 
-	hudson_lpc_port80();
-
 	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
 	 *  even though the register is not documented in the Kabini BKDG.

src/mainboard/hp/abm/Kconfig

@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY16_KB
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+	select DEFAULT_POST_ON_LPC
 	select SUPERIO_NUVOTON_NCT5104D
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE

src/mainboard/hp/abm/romstage.c

@@ -32,8 +32,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);
 
-	hudson_lpc_port80();
-
 	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
 	 *  even though the register is not documented in the Kabini BKDG.

src/mainboard/hp/pavilion_m6_1035dx/Kconfig

@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY15_TN
 	select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
 	select SOUTHBRIDGE_AMD_AGESA_HUDSON
+	select DEFAULT_POST_ON_LPC
 	select EC_COMPAL_ENE932
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE

src/mainboard/hp/pavilion_m6_1035dx/romstage.c

@@ -18,5 +18,4 @@
 
 void board_BeforeAgesa(struct sysinfo *cb)
 {
-	hudson_lpc_port80();
 }

src/mainboard/lenovo/g505s/Kconfig

@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_AGESA_FAMILY15_TN
 	select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
 	select SOUTHBRIDGE_AMD_AGESA_HUDSON
+	select DEFAULT_POST_ON_LPC
 	select EC_COMPAL_ENE932
 	select HAVE_OPTION_TABLE
 	select HAVE_MP_TABLE

src/mainboard/lenovo/g505s/romstage.c

@@ -18,5 +18,4 @@
 
 void board_BeforeAgesa(struct sysinfo *cb)
 {
-	hudson_lpc_port80();
 }

src/mainboard/msi/ms7721/romstage.c

@@ -117,11 +117,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	u8 byte;
 	pci_devfn_t dev;
 
-	if (CONFIG(POST_DEVICE_PCI_PCIE))
-		hudson_pci_port80();
-	else if (CONFIG(POST_DEVICE_LPC))
-		hudson_lpc_port80();
-
 	/* enable SIO LPC decode */
 	dev = PCI_DEV(0, 0x14, 3);
 	byte = pci_read_config8(dev, 0x48);

src/mainboard/pcengines/apu2/Kconfig

@@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select CPU_AMD_PI_00730F01
 	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_PI_AVALON
+	select DEFAULT_POST_ON_LPC
 	select SUPERIO_NUVOTON_NCT5104D
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/pcengines/apu2/romstage.c

@@ -52,8 +52,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	outb(0xd2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	hudson_lpc_port80();
-
 	post_code(0x30);
 	early_lpc_init();
 

src/southbridge/amd/agesa/hudson/bootblock.c

@@ -77,6 +77,11 @@ void bootblock_soc_early_init(void)
 	hudson_lpc_decode();
 	enable_acpimmio_decode_pm24();
 
+	if (CONFIG(POST_DEVICE_PCI_PCIE))
+		hudson_pci_port80();
+	else if (CONFIG(POST_DEVICE_LPC))
+		hudson_lpc_port80();
+
 	dev = PCI_DEV(0, 0x14, 3);
 	data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
 	/* enable 0x2e/0x4e IO decoding for SuperIO */

src/southbridge/amd/pi/hudson/bootblock.c

@@ -79,6 +79,11 @@ void bootblock_soc_early_init(void)
 	else
 		enable_acpimmio_decode_pm04();
 
+	if (CONFIG(POST_DEVICE_PCI_PCIE))
+		hudson_pci_port80();
+	else if (CONFIG(POST_DEVICE_LPC))
+		hudson_lpc_port80();
+
 	dev = PCI_DEV(0, 0x14, 3);
 	data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
 	/* enable 0x2e/0x4e IO decoding for SuperIO */