657d68bddc
Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
87 lines
1.7 KiB
Plaintext
87 lines
1.7 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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config BOARD_ODE_E21XX
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def_bool n
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if BOARD_ODE_E21XX
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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#select BINARYPI_LEGACY_WRAPPER
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select ROMCC_BOOTBLOCK
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select CPU_AMD_PI_00730F01
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select NORTHBRIDGE_AMD_PI_00730F01
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select SOUTHBRIDGE_AMD_PI_AVALON
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select DEFAULT_POST_ON_LPC
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_8192
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select GFXUMA
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select SUPERIO_FINTEK_F81866D
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config MAINBOARD_DIR
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string
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default "bap/ode_e21XX"
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config MAINBOARD_PART_NUMBER
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string
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default "ODE_E21XX"
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config MAX_CPUS
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int
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default 4
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config IRQ_SLOT_COUNT
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int
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default 11
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config HUDSON_LEGACY_FREE
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bool
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default y
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choice
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prompt "Select DDR3 clock"
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default BAP_E21_DDR3_1333
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help
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Select your preferenced DDR3 clock setting.
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Note: This option changes the total power consumption.
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If unsure, use DDR3-1333.
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config BAP_E21_DDR3_800
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bool "Select DDR3-800"
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config BAP_E21_DDR3_1066
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bool "Select DDR3-1066"
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config BAP_E21_DDR3_1333
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bool "Select DDR3-1333"
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endchoice
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config DIMM_SPD_SIZE
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int
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default 128
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endif # BOARD_ODE_E21XX
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