AGESA,binaryPI: Move PORT80 selection to C bootblock

Because the function is implemented in C, post_code() calls
from cache_as_ram.S and other early assembly entry files may
not currently work for cold boots. Assembly implementation
needs to follow one day.

This effectively removes PORT80 routing from boards with
ROMCC_BOOTBLOCK.

Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Kyösti Mälkki
2019-12-03 12:36:09 +02:00
parent dafc78bb8d
commit 657d68bddc
40 changed files with 32 additions and 47 deletions

View File

@@ -58,12 +58,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
if (CONFIG(POST_DEVICE_PCI_PCIE))
hudson_pci_port80();
if (CONFIG(POST_DEVICE_LPC))
hudson_lpc_port80();
/* enable SIO LPC decode */
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */

View File

@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
select DEFAULT_POST_ON_LPC
select SUPERIO_ITE_IT8728F
config MAINBOARD_DIR

View File

@@ -89,8 +89,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev2, 0x44, 0xff03ffd5);
hudson_lpc_port80();
/* Enable the AcpiMmio space */
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);