AGESA,binaryPI: Move PORT80 selection to C bootblock
Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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@@ -58,12 +58,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
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pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
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pci_write_config32(dev, 0x44, 0xff03ffd5);
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if (CONFIG(POST_DEVICE_PCI_PCIE))
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hudson_pci_port80();
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if (CONFIG(POST_DEVICE_LPC))
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hudson_lpc_port80();
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/* enable SIO LPC decode */
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byte = pci_read_config8(dev, 0x48);
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byte |= 3; /* 2e, 2f */
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@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_ACPI_TABLES
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select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
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select SOUTHBRIDGE_AMD_AGESA_YANGTZE
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select DEFAULT_POST_ON_LPC
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select SUPERIO_ITE_IT8728F
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config MAINBOARD_DIR
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@@ -89,8 +89,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
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pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
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pci_write_config32(dev2, 0x44, 0xff03ffd5);
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hudson_lpc_port80();
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/* Enable the AcpiMmio space */
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outb(0x24, 0xcd6);
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outb(0x1, 0xcd7);
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