cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
The lowest bound for L2 cache size on Socket P is 512 KiB. This allows the use of cbfs mcache on all platforms. This fixes building when some debug options are enabled. Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@@ -12,7 +12,7 @@ config DCACHE_RAM_BASE
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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default 0x10000
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config DCACHE_BSP_STACK_SIZE
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hex
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@@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500
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select INTEL_GMA_HAVE_VBT
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select NO_CBFS_MCACHE
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config VBOOT
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select VBOOT_VBNV_CMOS
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