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mb/system76: Clean up dsdt.asl

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- Use ACPI_DSDT_REV_2 instead of hard-coded value
- Update thelio-b1 to match other boards

Change-Id: I62bf9bfc4114c581bd0ec02d5a081d582a7aef32
This commit is contained in:
Tim Crawford 2021-01-27 09:48:30 -07:00 committed by Jeremy Soller
parent f32ef3e031
commit 67d15c2b28
3 changed files with 9 additions and 31 deletions
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2
src/mainboard/system76/gaze14/dsdt.asl
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@ -4,7 +4,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0 and up
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 // OEM revision

2
src/mainboard/system76/kbl-u/dsdt.asl
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@ -4,7 +4,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0 and up
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 // OEM revision

36
src/mainboard/system76/thelio-b1/dsdt.asl
View File

@ -1,51 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 System76
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0 and up
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 // OEM revision
)
{
// Some generic macros
#include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/cannonlake/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl>
}
Device (\_SB.PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl>
}
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <drivers/pc80/pc/ps2_controller.asl>
}
}