mb/system76/gaze17: Update 3050 variant
Change-Id: I8d8bb8345816a039ed5bbe7ca74a122cd6005960 Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
committed by
Tim Crawford
parent
2b030e54fd
commit
682621fa1f
@@ -66,7 +66,6 @@ chip soc/intel/alderlake
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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chip drivers/gfx/nvidia
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device pci 00.0 on end # VGA controller
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@@ -75,50 +74,13 @@ chip soc/intel/alderlake
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device pci 00.3 on end # USB Type-C UCSI controller
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end
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end
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device ref igpu on
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# DDIA is eDP
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register "ddi_portA_config" = "1"
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register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
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end
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device ref pcie4_0 on
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# PCIe PEG0 x4, Clock 0 (SSD2)
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_src = 0,
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.clk_req = 0,
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.flags = PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD1_RST#
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register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ#
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device generic 0 on end
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end
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end
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device ref tbt_pcie_rp0 on end
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device ref tcss_xhci on
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
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device ref tcss_root_hub on
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device ref tcss_usb3_port1 on end
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end
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end
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device ref tcss_dma0 on end
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# From PCH EDS(TODO)
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device ref xhci on
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
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end
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device ref shared_sram on end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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@@ -130,7 +92,15 @@ chip soc/intel/alderlake
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# Touchpad I2C bus
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register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
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chip drivers/i2c/hid
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register "generic.hid" = ""PNP0C50""
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register "generic.hid" = ""ELAN0412""
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register "generic.desc" = ""ELAN Touchpad""
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register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
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register "generic.probed" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 15 on end
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end
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chip drivers/i2c/hid
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register "generic.hid" = ""FTCS1000""
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register "generic.desc" = ""FocalTech Touchpad""
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register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
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register "generic.probed" = "1"
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@@ -143,62 +113,6 @@ chip soc/intel/alderlake
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register "sata_ports_enable[1]" = "1" # SSD2 (SATA1A)
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register "sata_ports_dev_slp[1]" = "1" # GPP_H13 (DEVSLP1B)
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end
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device ref pcie_rp5 on
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# PCIe root port #5 x1, Clock 2 (WLAN)
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" # M2_WLAN_RST#
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register "srcclk_pin" = "2" # WLAN_CLKREQ#
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device generic 0 on end
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end
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end
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device ref pcie_rp6 on
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# PCIe root port #6 x1, Clock 5 (CARD)
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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chip soc/intel/common/block/pcie/rtd3
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# XXX: No enable_gpio = no D3cold?
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # CARD_RTD3_RST#
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register "srcclk_pin" = "5" # CARD_CLKREQ#
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device generic 0 on end
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end
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end
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device ref pcie_rp7 on
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# PCIe root port #7 x1, Clock 6 (GLAN)
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# Clock source is shared with LAN and hence marked as free running.
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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.clk_src = 6,
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.clk_req = 6,
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.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
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end
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device ref pcie_rp9 on
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# PCIe root port #9 x4, Clock 1 (SSD1)
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_PCH_SSD_RST#
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register "srcclk_pin" = "1" # SSD_CLKREQ#
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device generic 0 on end
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end
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end
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device ref pch_espi on
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register "gen1_dec" = "0x00040069" # EC PM channel
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register "gen2_dec" = "0x00fc0E01" # AP/EC command
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@@ -8,10 +8,13 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
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params->CnviClkreqPinMux = 0x394CE605; // GPP_F5
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params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
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params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
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params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
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params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6
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params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7
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params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 (DEVSLP1B)
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params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12
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params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
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variant_configure_gpios();
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}
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@@ -33,10 +33,10 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_A11, NONE),
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PAD_NC(GPP_A12, NONE),
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PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
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PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14
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//PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // PCH_DP_HPD
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
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_PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000), // TP_ATTN#
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PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
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PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH
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PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE#
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@@ -102,10 +102,10 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_D2, NONE),
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PAD_NC(GPP_D3, NONE),
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PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
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PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
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PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
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//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
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//PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
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//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
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//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
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PAD_NC(GPP_D9, NONE),
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PAD_NC(GPP_D10, NONE),
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PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK
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@@ -120,10 +120,10 @@ static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPP_E ------- */
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PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
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_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
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//_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
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PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
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PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
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//PAD_CFG_GP0(GPP_E4, 0, DEEP), // DGPU_PWR_EN
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PAD_NC(GPP_E4, NONE),
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PAD_NC(GPP_E5, NONE),
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PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6_STRAP
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PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
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@@ -150,7 +150,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
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PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
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PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
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//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
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PAD_NC(GPP_F7, NONE),
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//PAD_NC(GPP_F8, NONE),
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@@ -164,7 +164,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
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PAD_NC(GPP_F17, NONE),
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PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ#
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//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ#
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PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
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PAD_NC(GPP_F21, NONE),
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL
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@@ -181,8 +181,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_H7, NONE, DEEP), // PCH_I2C_SCL
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PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
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PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
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//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
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//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
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PAD_NC(GPP_H12, NONE),
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_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1
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//PAD_NC(GPP_H14, NONE),
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@@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // PM_CLKRUN#
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PAD_NC(GPP_H21, NONE),
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PAD_NC(GPP_H22, NONE),
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PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
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//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
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/* ------- GPIO Group GPP_R ------- */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
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@@ -4,8 +4,10 @@
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#include <soc/gpio.h>
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static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPO(GPP_E4, 0, DEEP), // DGPU_PWR_EN
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PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
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PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
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};
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void variant_configure_early_gpios(void)
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@@ -20,6 +20,10 @@ const u32 cim_verb_data[] = {
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AZALIA_PIN_CFG(0, 0x21, 0x02211020),
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};
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const u32 pc_beep_verbs[] = {};
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const u32 pc_beep_verbs[] = {
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// Adjust mic coefficient
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0x02050007,
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0x02040202,
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};
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AZALIA_ARRAY_SIZES;
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@@ -6,7 +6,7 @@
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#include <soc/gpio.h>
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#define DGPU_RST_N GPP_B2
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#define DGPU_PWR_EN GPP_E4
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#define DGPU_PWR_EN GPP_A14
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#define DGPU_GC6 GPP_F13
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#define DGPU_SSID 0x866d1558
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@@ -1,5 +1,103 @@
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chip soc/intel/alderlake
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device domain 0 on
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subsystemid 0x1558 0x866d inherit
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device ref igpu on
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# DDIA is eDP
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register "ddi_portA_config" = "1"
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register "ddi_ports_config" = "{
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[DDI_PORT_A] = DDI_ENABLE_HPD,
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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}"
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end
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device ref pcie4_0 on
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# PCIe PEG0 x4, Clock 0 (SSD2)
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_src = 0,
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.clk_req = 0,
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.flags = PCIE_RP_LTR,
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}"
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chip soc/intel/common/block/pcie/rtd3
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# XXX: Enable tied to 3.3VS?
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#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
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register "srcclk_pin" = "0" # SSD0_CLKREQ#
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device generic 0 on end
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end
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end
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device ref xhci on
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# USB2
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
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register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
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end
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device ref pcie_rp5 on
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# PCIe RP#5 x4, Clock 1 (SSD)
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_LTR,
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}"
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chip soc/intel/common/block/pcie/rtd3
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# XXX: Enable tied to 3.3VS?
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#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
|
||||
register "srcclk_pin" = "1" # SSD1_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# PCIe RP#9 x1, Clock 6 (GLAN)
|
||||
register "pch_pcie_rp[PCH_RP(9)]" = "{
|
||||
.clk_src = 6,
|
||||
.clk_req = 6,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
# XXX: Enable tied to VDD3?
|
||||
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
|
||||
register "srcclk_pin" = "6" # GLAN_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp10 on
|
||||
# PCIe RP#10 x1, Clock 2 (WLAN)
|
||||
register "pch_pcie_rp[PCH_RP(10)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
|
||||
register "srcclk_pin" = "2" # WLAN_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp11 on
|
||||
# PCIe RP#11 x1, Clock 5 (CARD)
|
||||
register "pch_pcie_rp[PCH_RP(11)]" = "{
|
||||
.clk_src = 5,
|
||||
.clk_req = 5,
|
||||
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
# XXX: Enable tied to 3.3VS?
|
||||
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B7)" # CARD_PWR_EN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
|
||||
register "srcclk_pin" = "5" # CARD_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
@@ -2,6 +2,93 @@ chip soc/intel/alderlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x867c inherit
|
||||
|
||||
device ref igpu on
|
||||
# DDIA is eDP
|
||||
register "ddi_portA_config" = "1"
|
||||
register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
|
||||
end
|
||||
device ref pcie4_0 on
|
||||
# PCIe PEG0 x4, Clock 0 (SSD2)
|
||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||
.clk_src = 0,
|
||||
.clk_req = 0,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD1_RST#
|
||||
register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref tbt_pcie_rp0 on end
|
||||
device ref tcss_dma0 on end
|
||||
device ref xhci on
|
||||
# USB2
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
# USB3
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
|
||||
end
|
||||
device ref pcie_rp5 on
|
||||
# PCIe root port #5 x1, Clock 2 (WLAN)
|
||||
register "pch_pcie_rp[PCH_RP(5)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" # M2_WLAN_RST#
|
||||
register "srcclk_pin" = "2" # WLAN_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp6 on
|
||||
# PCIe root port #6 x1, Clock 5 (CARD)
|
||||
register "pch_pcie_rp[PCH_RP(6)]" = "{
|
||||
.clk_src = 5,
|
||||
.clk_req = 5,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
# XXX: No enable_gpio = no D3cold?
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # CARD_RTD3_RST#
|
||||
register "srcclk_pin" = "5" # CARD_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp7 on
|
||||
# PCIe root port #7 x1, Clock 6 (GLAN)
|
||||
# Clock source is shared with LAN and hence marked as free running.
|
||||
register "pch_pcie_rp[PCH_RP(7)]" = "{
|
||||
.clk_src = 6,
|
||||
.clk_req = 6,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
|
||||
}"
|
||||
register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# PCIe root port #9 x4, Clock 1 (SSD1)
|
||||
register "pch_pcie_rp[PCH_RP(9)]" = "{
|
||||
.clk_src = 1,
|
||||
.clk_req = 1,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_PCH_SSD_RST#
|
||||
register "srcclk_pin" = "1" # SSD_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref gbe on end
|
||||
end
|
||||
end
|
||||
|
Reference in New Issue
Block a user