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mb/system76/gaze17: Update 3050 variant

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Change-Id: I8d8bb8345816a039ed5bbe7ca74a122cd6005960
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-07-07 14:35:15 -06:00
committed by Tim Crawford
parent 2b030e54fd
commit 682621fa1f
8 changed files with 221 additions and 113 deletions
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104
src/mainboard/system76/gaze17/devicetree.cb
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@@ -66,7 +66,6 @@ chip soc/intel/alderlake
.clk_src = 3, .clk_src = 3,
.clk_req = 3, .clk_req = 3,
.flags = PCIE_RP_LTR, .flags = PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
}" }"
chip drivers/gfx/nvidia chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller device pci 00.0 on end # VGA controller
@@ -75,50 +74,13 @@ chip soc/intel/alderlake
device pci 00.3 on end # USB Type-C UCSI controller device pci 00.3 on end # USB Type-C UCSI controller
end end
end end
device ref igpu on
# DDIA is eDP
register "ddi_portA_config" = "1"
register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
end
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD1_RST#
register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ#
device generic 0 on end
end
end
device ref tbt_pcie_rp0 on end
device ref tcss_xhci on device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
device ref tcss_root_hub on device ref tcss_root_hub on
device ref tcss_usb3_port1 on end device ref tcss_usb3_port1 on end
end end
end end
device ref tcss_dma0 on end
# From PCH EDS(TODO)
device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
end
device ref shared_sram on end device ref shared_sram on end
device ref cnvi_wifi on device ref cnvi_wifi on
chip drivers/wifi/generic chip drivers/wifi/generic
@@ -130,7 +92,15 @@ chip soc/intel/alderlake
# Touchpad I2C bus # Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50"" register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad"" register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.probed" = "1" register "generic.probed" = "1"
@@ -143,62 +113,6 @@ chip soc/intel/alderlake
register "sata_ports_enable[1]" = "1" # SSD2 (SATA1A) register "sata_ports_enable[1]" = "1" # SSD2 (SATA1A)
register "sata_ports_dev_slp[1]" = "1" # GPP_H13 (DEVSLP1B) register "sata_ports_dev_slp[1]" = "1" # GPP_H13 (DEVSLP1B)
end end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" # M2_WLAN_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: No enable_gpio = no D3cold?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # CARD_RTD3_RST#
register "srcclk_pin" = "5" # CARD_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 6 (GLAN)
# Clock source is shared with LAN and hence marked as free running.
register "pch_pcie_rp[PCH_RP(7)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
}"
register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 1 (SSD1)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_PCH_SSD_RST#
register "srcclk_pin" = "1" # SSD_CLKREQ#
device generic 0 on end
end
end
device ref pch_espi on device ref pch_espi on
register "gen1_dec" = "0x00040069" # EC PM channel register "gen1_dec" = "0x00040069" # EC PM channel
register "gen2_dec" = "0x00fc0E01" # AP/EC command register "gen2_dec" = "0x00fc0E01" # AP/EC command

7
src/mainboard/system76/gaze17/ramstage.c
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@@ -8,10 +8,13 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
params->CnviRfResetPinMux = 0x194CE404; // GPP_F4 params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
params->CnviClkreqPinMux = 0x394CE605; // GPP_F5 params->CnviClkreqPinMux = 0x394CE605; // GPP_F5
params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6
params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7
params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 (DEVSLP1B) params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12
params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
variant_configure_gpios(); variant_configure_gpios();
} }

26
src/mainboard/system76/gaze17/variants/3050/gpio.c
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@@ -33,10 +33,10 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_A11, NONE), PAD_NC(GPP_A11, NONE),
PAD_NC(GPP_A12, NONE), PAD_NC(GPP_A12, NONE),
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14 //PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // PCH_DP_HPD PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // PCH_DP_HPD
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3# PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
_PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000), // TP_ATTN# PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH
PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE# PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE#
@@ -102,10 +102,10 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_D2, NONE), PAD_NC(GPP_D2, NONE),
PAD_NC(GPP_D3, NONE), PAD_NC(GPP_D3, NONE),
PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ# //PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ# //PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ# //PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ# //PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
PAD_NC(GPP_D9, NONE), PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE), PAD_NC(GPP_D10, NONE),
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK
@@ -120,10 +120,10 @@ static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPP_E ------- */ /* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE# PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# //_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2 PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
//PAD_CFG_GP0(GPP_E4, 0, DEEP), // DGPU_PWR_EN PAD_NC(GPP_E4, NONE),
PAD_NC(GPP_E5, NONE), PAD_NC(GPP_E5, NONE),
PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6_STRAP PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6_STRAP
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
@@ -150,7 +150,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST# PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ //PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_NC(GPP_F7, NONE), PAD_NC(GPP_F7, NONE),
//PAD_NC(GPP_F8, NONE), //PAD_NC(GPP_F8, NONE),
@@ -164,7 +164,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT# PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
PAD_NC(GPP_F17, NONE), PAD_NC(GPP_F17, NONE),
PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ# //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ#
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1# PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
PAD_NC(GPP_F21, NONE), PAD_NC(GPP_F21, NONE),
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL
@@ -181,8 +181,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_H7, NONE, DEEP), // PCH_I2C_SCL PAD_CFG_GPI(GPP_H7, NONE, DEEP), // PCH_I2C_SCL
PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX //PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX //PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
PAD_NC(GPP_H12, NONE), PAD_NC(GPP_H12, NONE),
_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1 _PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1
//PAD_NC(GPP_H14, NONE), //PAD_NC(GPP_H14, NONE),
@@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // PM_CLKRUN# PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_NC(GPP_H21, NONE), PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE), PAD_NC(GPP_H22, NONE),
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ# //PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
/* ------- GPIO Group GPP_R ------- */ /* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK

4
src/mainboard/system76/gaze17/variants/3050/gpio_early.c
View File

@@ -4,8 +4,10 @@
#include <soc/gpio.h> #include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_E4, 0, DEEP), // DGPU_PWR_EN PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
}; };
void variant_configure_early_gpios(void) void variant_configure_early_gpios(void)

6
src/mainboard/system76/gaze17/variants/3050/hda_verb.c
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@@ -20,6 +20,10 @@ const u32 cim_verb_data[] = {
AZALIA_PIN_CFG(0, 0x21, 0x02211020), AZALIA_PIN_CFG(0, 0x21, 0x02211020),
}; };
const u32 pc_beep_verbs[] = {}; const u32 pc_beep_verbs[] = {
// Adjust mic coefficient
0x02050007,
0x02040202,
};
AZALIA_ARRAY_SIZES; AZALIA_ARRAY_SIZES;

2
src/mainboard/system76/gaze17/variants/3050/include/variant/gpio.h
View File

@@ -6,7 +6,7 @@
#include <soc/gpio.h> #include <soc/gpio.h>
#define DGPU_RST_N GPP_B2 #define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_E4 #define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_F13 #define DGPU_GC6 GPP_F13
#define DGPU_SSID 0x866d1558 #define DGPU_SSID 0x866d1558

98
src/mainboard/system76/gaze17/variants/3050/overridetree.cb
View File

@@ -1,5 +1,103 @@
chip soc/intel/alderlake chip soc/intel/alderlake
device domain 0 on device domain 0 on
subsystemid 0x1558 0x866d inherit subsystemid 0x1558 0x866d inherit
device ref igpu on
# DDIA is eDP
register "ddi_portA_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
end
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "0" # SSD0_CLKREQ#
device generic 0 on end
end
end
device ref xhci on
# USB2
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
end
device ref pcie_rp5 on
# PCIe RP#5 x4, Clock 1 (SSD)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "1" # SSD1_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp9 on
# PCIe RP#9 x1, Clock 6 (GLAN)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to VDD3?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "6" # GLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp10 on
# PCIe RP#10 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(10)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp11 on
# PCIe RP#11 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(11)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B7)" # CARD_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "5" # CARD_CLKREQ#
device generic 0 on end
end
end
end end
end end

87
src/mainboard/system76/gaze17/variants/3060/overridetree.cb
View File

@@ -2,6 +2,93 @@ chip soc/intel/alderlake
device domain 0 on device domain 0 on
subsystemid 0x1558 0x867c inherit subsystemid 0x1558 0x867c inherit
device ref igpu on
# DDIA is eDP
register "ddi_portA_config" = "1"
register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
end
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD1_RST#
register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ#
device generic 0 on end
end
end
device ref tbt_pcie_rp0 on end
device ref tcss_dma0 on end
device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" # M2_WLAN_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: No enable_gpio = no D3cold?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # CARD_RTD3_RST#
register "srcclk_pin" = "5" # CARD_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 6 (GLAN)
# Clock source is shared with LAN and hence marked as free running.
register "pch_pcie_rp[PCH_RP(7)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
}"
register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 1 (SSD1)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_PCH_SSD_RST#
register "srcclk_pin" = "1" # SSD_CLKREQ#
device generic 0 on end
end
end
device ref gbe on end device ref gbe on end
end end
end end