cpu/intel/model_1067x: Add proper c-state/p-state/thermal support
Change-Id: I853454e8f5617fb7af5dddd7288bdeeacc7b1b8e Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Nico Huber
Stefan Reinauer
parent
bf10bc3e44
commit
68d7c7aa8b
24
src/cpu/intel/model_1067x/chip.h
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24
src/cpu/intel/model_1067x/chip.h
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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struct cpu_intel_model_1067x_config {
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int c5 : 1;
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int c6 : 1;
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int slfm : 1;
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};
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -33,6 +34,8 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/name.h>
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#include "chip.h"
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static const uint32_t microcode_updates[] = {
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#include "microcode-2618-m441067AA07.h"
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#include "microcode-2626-m1010677705.h"
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@ -98,20 +101,45 @@ static void enable_vmx(void)
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#define PMG_CST_CONFIG_CONTROL 0xe2
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#define PMG_IO_BASE_ADDR 0xe3
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#define PMG_IO_CAPTURE_ADDR 0xe4
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#define MSR_BBL_CR_CTL3 0x11e
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#define MSR_FSB_FREQ 0xcd
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#define CST_RANGE 2
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static void configure_c_states(void)
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static void configure_c_states(const int quad)
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{
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msr_t msr;
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/* Find pointer to CPU configuration. */
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const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
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const struct cpu_intel_model_1067x_config *const conf =
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(lapic && lapic->chip_info) ? lapic->chip_info : NULL;
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/* Is C5 requested and supported? */
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const int c5 = conf && conf->c5 &&
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(rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) &&
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!(rdmsr(MSR_FSB_FREQ).lo & (1 << 31));
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/* Is C6 requested and supported? */
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const int c6 = conf && conf->c6 &&
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((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5;
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const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */
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msr = rdmsr(PMG_CST_CONFIG_CONTROL);
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msr.lo |= (1 << 15); // config lock until next reset
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msr.lo |= (1 << 14); // Deeper Sleep
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msr.lo |= (1 << 10); // Enable IO MWAIT redirection
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msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
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msr.lo |= (1 << 3); // Dynamic L2
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msr.lo |= (1 << 8);
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if (quad) {
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msr.lo = (msr.lo & ~(7 << 0)) | (4 << 0);
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}
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if (c5) {
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msr.lo &= ~(1 << 13);
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msr.lo &= ~(7 << 0);
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msr.lo |= (1 << 3); /* Enable dynamic L2. */
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msr.lo |= (1 << 14); /* Enable deeper sleep */
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}
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/* Next two fields seem to be mutually exclusive: */
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msr.lo &= ~(7 << 4);
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msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */
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if (c6)
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msr.lo |= (1 << 25);
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wrmsr(PMG_CST_CONFIG_CONTROL, msr);
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/* Set Processor MWAIT IO BASE */
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@ -121,52 +149,160 @@ static void configure_c_states(void)
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/* Set IO Capture Address */
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msr.hi = 0;
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msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16);
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msr.lo = ((PMB0_BASE + 4) & 0xffff) | ((cst_range & 0xffff) << 16);
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wrmsr(PMG_IO_CAPTURE_ADDR, msr);
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if (c5) {
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msr = rdmsr(MSR_BBL_CR_CTL3);
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msr.lo &= ~(7 << 25);
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msr.lo |= (2 << 25);
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msr.lo &= ~(3 << 30);
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msr.lo |= (1 << 30);
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wrmsr(MSR_BBL_CR_CTL3, msr);
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}
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}
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#define IA32_MISC_ENABLE 0x1a0
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static void configure_misc(void)
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static void configure_p_states(const char stepping, const char cores)
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{
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msr_t msr;
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 3); /* TM1 enable */
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msr.lo |= (1 << 13); /* TM2 enable */
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/* Find pointer to CPU configuration. */
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const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
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struct cpu_intel_model_1067x_config *const conf =
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(lapic && lapic->chip_info) ? lapic->chip_info : NULL;
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msr = rdmsr(MSR_EXTENDED_CONFIG);
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if (conf->slfm && (msr.lo & (1 << 27))) /* Super LFM supported? */
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msr.lo |= (1 << 28); /* Enable Super LFM. */
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wrmsr(MSR_EXTENDED_CONFIG, msr);
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if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) {
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/* Turbo supported? */
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if ((stepping == 0xa) && (cores < 4)) {
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msr = rdmsr(MSR_FSB_FREQ);
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msr.lo |= (1 << 3); /* Enable hysteresis. */
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wrmsr(MSR_FSB_FREQ, msr);
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}
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msr = rdmsr(IA32_PERF_CTL);
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msr.hi &= ~(1 << (32 - 32)); /* Clear turbo disable. */
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wrmsr(IA32_PERF_CTL, msr);
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}
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msr = rdmsr(PMG_CST_CONFIG_CONTROL);
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msr.lo &= ~(1 << 11); /* Enable hw coordination. */
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msr.lo |= (1 << 15); /* Lock config until next reset. */
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wrmsr(PMG_CST_CONFIG_CONTROL, msr);
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}
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#define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x))
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#define MSR_EMTTM_TABLE_NUM 6
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static void configure_emttm_tables(void)
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{
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int i;
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int num_states, pstate_idx;
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msr_t msr;
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sst_table_t pstates;
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/* Gather p-state information. */
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speedstep_gen_pstates(&pstates);
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/* Never turbo mode or Super LFM. */
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num_states = pstates.num_states;
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if (pstates.states[0].is_turbo)
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--num_states;
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if (pstates.states[pstates.num_states - 1].is_slfm)
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--num_states;
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/* Repeat lowest p-state if we haven't enough states. */
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const int num_lowest_pstate =
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(num_states < MSR_EMTTM_TABLE_NUM)
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? (MSR_EMTTM_TABLE_NUM - num_states) + 1
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: 1;
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/* Start from the lowest entry but skip Super LFM. */
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if (pstates.states[pstates.num_states - 1].is_slfm)
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pstate_idx = pstates.num_states - 2;
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else
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pstate_idx = pstates.num_states - 1;
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for (i = 0; i < MSR_EMTTM_TABLE_NUM; ++i) {
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if (i >= num_lowest_pstate)
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--pstate_idx;
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const sst_state_t *const pstate = &pstates.states[pstate_idx];
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printk(BIOS_DEBUG, "writing P-State %d: %d, %d, "
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"%2d, 0x%02x, %d; encoded: 0x%04x\n",
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pstate_idx, pstate->dynfsb, pstate->nonint,
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pstate->ratio, pstate->vid, pstate->power,
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SPEEDSTEP_ENCODE_STATE(*pstate));
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msr.hi = 0;
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msr.lo = SPEEDSTEP_ENCODE_STATE(pstates.states[pstate_idx]) &
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/* Don't set half ratios. */
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~SPEEDSTEP_RATIO_NONINT;
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wrmsr(MSR_EMTTM_CR_TABLE(i), msr);
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}
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msr = rdmsr(MSR_EMTTM_CR_TABLE(5));
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msr.lo |= (1 << 31); /* lock tables */
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wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
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}
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static void configure_misc(const int eist, const int tm2, const int emttm)
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{
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msr_t msr;
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const u32 sub_cstates = cpuid_edx(5);
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msr = rdmsr(IA32_MISC_ENABLES);
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msr.lo |= (1 << 3); /* TM1 enable */
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if (tm2)
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msr.lo |= (1 << 13); /* TM2 enable */
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msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */
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msr.lo |= (1 << 18); /* MONITOR/MWAIT enable */
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msr.lo |= (1 << 10); /* FERR# multiplexing */
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// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
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msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
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if (eist)
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msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
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/* Enable C2E */
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msr.lo |= (1 << 26);
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if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) {
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msr.lo |= (1 << 26);
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}
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/* Enable C4E */
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/* TODO This should only be done on mobile CPUs, see cpuid 5 */
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msr.hi |= (1 << (32 - 32)); // C4E
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msr.hi |= (1 << (33 - 32)); // Hard C4E
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if (((sub_cstates >> (4 * 4)) & 0xf) >= 2) {
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msr.hi |= (1 << (32 - 32)); // C4E
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msr.hi |= (1 << (33 - 32)); // Hard C4E
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}
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/* Enable EMTTM. */
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/* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */
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msr.hi |= (1 << (36 - 32));
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/* Enable EMTTM */
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if (emttm)
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msr.hi |= (1 << (36 - 32));
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wrmsr(IA32_MISC_ENABLE, msr);
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/* Enable turbo mode */
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if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32)))
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msr.hi &= ~(1 << (38 - 32));
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msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
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wrmsr(IA32_MISC_ENABLE, msr);
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wrmsr(IA32_MISC_ENABLES, msr);
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if (eist) {
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msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
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wrmsr(IA32_MISC_ENABLES, msr);
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}
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}
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#define PIC_SENS_CFG 0x1aa
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static void configure_pic_thermal_sensors(void)
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static void configure_pic_thermal_sensors(const int tm2, const int quad)
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{
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msr_t msr;
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msr = rdmsr(PIC_SENS_CFG);
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if (quad)
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msr.lo |= (1 << 31);
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else
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msr.lo &= ~(1 << 31);
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if (tm2)
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msr.lo |= (1 << 20); /* Enable TM1 if TM2 fails. */
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msr.lo |= (1 << 21); // inter-core lock TM1
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msr.lo |= (1 << 4); // Enable bypass filter
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msr.lo |= (1 << 4); // Enable bypass filter /* What does it do? */
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wrmsr(PIC_SENS_CFG, msr);
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}
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@ -179,6 +315,30 @@ static void model_1067x_init(device_t cpu)
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{
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char processor_name[49];
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/* Gather some information: */
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const struct cpuid_result cpuid1 = cpuid(1);
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/* Read stepping. */
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const char stepping = cpuid1.eax & 0xf;
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/* Read number of cores. */
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const char cores = (cpuid1.ebx >> 16) & 0xf;
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/* Is this a quad core? */
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const char quad = cores > 2;
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/* Is this even a multiprocessor? */
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const char mp = cores > 1;
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/* Enable EMTTM on uni- and on multi-processors if it's not disabled. */
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const char emttm = !mp || !(rdmsr(MSR_EXTENDED_CONFIG).lo & 4);
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/* Is enhanced speedstep supported? */
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const char eist = (cpuid1.ecx & (1 << 7)) &&
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!(rdmsr(IA32_PLATFORM_ID).lo & (1 << 17));
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/* Test for TM2 only if EIST is available. */
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const char tm2 = eist && (cpuid1.ecx & (1 << 8));
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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@ -214,13 +374,20 @@ static void model_1067x_init(device_t cpu)
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enable_vmx();
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/* Configure C States */
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configure_c_states();
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configure_c_states(quad);
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/* Configure P States */
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configure_p_states(stepping, cores);
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/* EMTTM */
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if (emttm)
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configure_emttm_tables();
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/* Configure Enhanced SpeedStep and Thermal Sensors */
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configure_misc();
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configure_misc(eist, tm2, emttm);
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/* PIC thermal sensor control */
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configure_pic_thermal_sensors();
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configure_pic_thermal_sensors(tm2, quad);
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/* Start up my cpu siblings */
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intel_sibling_init(cpu);
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@ -242,3 +409,6 @@ static const struct cpu_driver driver __cpu_driver = {
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.id_table = cpu_table,
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};
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struct chip_operations cpu_intel_model_1067x_ops = {
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CHIP_NAME("Intel Penryn CPU")
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};
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@ -1 +1,2 @@
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ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c speedstep.c
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ramstage-$(CONFIG_CPU_INTEL_MODEL_1067X) += speedstep.c
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