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mb/system76/adl-p: Fix booting FSP debug build

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Fix assertions for SATA and I2C1 devices GPIOs.

TODO: Test on darp8.

Change-Id: I89dbd212a7dbd55c84d8ebbb7420b960da8175af
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-06-27 12:28:50 -06:00
committed by Tim Crawford
parent f56daffffc
commit 68d9b42b26
4 changed files with 9 additions and 3 deletions
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1
src/mainboard/system76/adl-p/devicetree.cb
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@@ -69,6 +69,7 @@ chip soc/intel/alderlake
device ref heci1 on end
device ref sata on
register "sata_salp_support" = "1"
register "sata_ports_enable[1]" = "1" # SSD1
register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
end

7
src/mainboard/system76/adl-p/ramstage.c
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@@ -8,10 +8,15 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
params->CnviClkreqPinMux = 0x394CE605; // GPP_F5
params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6
params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7
params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12
params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
params->SataPortsSolidStateDrive[1] = 1;
}
static void mainboard_init(void *chip_info)

2
src/mainboard/system76/adl-p/variants/darp8/gpio.c
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@@ -183,7 +183,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
_PAD_CFG_STRUCT(GPP_H12, 0x44001500, 0x0000), // SATA1_DEVSLP1
PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), // SATA1_DEVSLP1
PAD_NC(GPP_H13, NONE),
//PAD_CFG_GPI(GPP_H14, NONE, DEEP),
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK

2
src/mainboard/system76/adl-p/variants/lemp11/gpio.c
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@@ -183,7 +183,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
_PAD_CFG_STRUCT(GPP_H12, 0x44001500, 0x0000), // SATA1_DEVSLP1
PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), // SATA1_DEVSLP1
PAD_NC(GPP_H13, NONE),
//PAD_NC(GPP_H14, NONE),
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK