soc/amd/cezanne: Set up SoC-specific XHCI definitions
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67939 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -70,6 +70,7 @@ config SOC_AMD_CEZANNE
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select SOC_AMD_COMMON_FSP_DMI_TABLES
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select SOC_AMD_COMMON_FSP_PCI
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select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
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select SOC_AMD_COMMON_BLOCK_XHCI
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select SSE2
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select UDK_2017_BINDING
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select USE_DDR4
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17
src/soc/amd/cezanne/include/soc/xhci.h
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17
src/soc/amd/cezanne/include/soc/xhci.h
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@@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_CEZANNE_XHCI_H
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#define AMD_CEZANNE_XHCI_H
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#include <device/device.h>
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#define SOC_XHCI_0 DEV_PTR(xhci_0)
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#define SOC_XHCI_1 DEV_PTR(xhci_1)
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#define SOC_XHCI_2 NULL
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#define SOC_XHCI_3 NULL
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#define SOC_XHCI_4 NULL
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#define SOC_XHCI_5 NULL
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#define SOC_XHCI_6 NULL
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#define SOC_XHCI_7 NULL
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#endif /* AMD_CEZANNE_XHCI_H */
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