soc/intel/alderlake/hsphy: Add support for HSPHY firmware loading
BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init. Implementation based on Slimbootloader's "Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib" and FSP source. TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded and its recipe and version is printed. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080
This commit is contained in:
Michał Żygowski
committed by
Jeremy Soller
Jeremy Soller
parent
28cc4183c8
commit
6b56932606
@@ -34,6 +34,7 @@ ramstage-y += espi.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio.c
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ramstage-y += hsphy.c
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ramstage-y += lockdown.c
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ramstage-y += me.c
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ramstage-y += p2sb.c
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@@ -12,6 +12,7 @@
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#include <intelblocks/itss.h>
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#include <intelblocks/pcie_rp.h>
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#include <intelblocks/xdci.h>
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#include <soc/hsphy.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/itss.h>
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#include <soc/pci_devs.h>
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@@ -156,6 +157,15 @@ static void soc_fill_gpio_pm_configuration(void)
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void soc_init_pre_device(void *chip_info)
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{
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if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_P)) {
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load_and_init_hsphy();
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if (is_devfn_enabled(SA_DEVFN_CPU_PCIE1_0))
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print_hsphy_version(SA_DEVFN_CPU_PCIE1_0);
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if (is_devfn_enabled(SA_DEVFN_CPU_PCIE1_1) &&
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CONFIG(SOC_INTEL_ALDERLAKE_PCH_S))
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print_hsphy_version(SA_DEVFN_CPU_PCIE1_1);
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}
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/* Perform silicon specific init. */
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fsp_silicon_init();
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344
src/soc/intel/alderlake/hsphy.c
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344
src/soc/intel/alderlake/hsphy.c
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@@ -0,0 +1,344 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define __SIMPLE_DEVICE__
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#include <assert.h>
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#include <stdlib.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/mmio.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/systemagent.h>
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#include <soc/hsphy.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <vb2_api.h>
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#include <lib.h>
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#include <delay.h>
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#define HASHALG_SHA1 0x00000001
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#define HASHALG_SHA256 0x00000002
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#define HASHALG_SHA384 0x00000003
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#define HASHALG_SHA512 0x00000004
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#define MAX_HASH_SIZE 64 // 64 is max size for SHA512
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#define GET_IP_FIRMWARE_CMD 0x21
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#define HSPHY_PAYLOAD_SIZE 32*KiB
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#define CPU_PID_PCIE_BUTTRESSx16_0 0x54
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#define CPU_PID_PCIE_PHYX16_BROADCAST 0x55
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#define CPU_PID_PCIE_PHYx16_0 0x56
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#define CPU_PID_PCIE_PHYx16_1 0x57
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#define HSPHY_LOADER_BASE 0
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#define HSPHY_VERIFIER_BASE 0x3000
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#define HSPHY_MEM_IP_CAP_0 (HSPHY_VERIFIER_BASE + 0x18)
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#define HSPHY_MEM_IP_CAP_0_BIOS_LOADER 12
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#define HSPHY_MEM_IP_CAP_0_MASK 0xF
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#define HSPHY_MEM_VERIFIER_ERROR_STATUS (HSPHY_VERIFIER_BASE + 0x30)
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#define HSPHY_MEM_VERIFIER_ERROR_STATUS_ERROR_CODE 4
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#define HSPHY_RECIPE_VERSION 0x314
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#define HSPHY_RECIPE_VERSION_MINOR_MASK 0xF
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#define HSPHY_RECIPE_VERSION_MINOR_OFFSET 0
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#define HSPHY_RECIPE_VERSION_MAJOR_MASK 0xF0
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#define HSPHY_RECIPE_VERSION_MAJOR_OFFSET 4
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#define HSPHY_FW_VERSION 0x1C
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#define HSPHY_FW_VERSION_PROD_MAJOR_MASK 0xF0000000
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#define HSPHY_FW_VERSION_PROD_MAJOR_OFFSET 28
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#define HSPHY_FW_VERSION_PROD_MINOR_MASK 0xFF00000
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#define HSPHY_FW_VERSION_PROD_MINOR_OFFSET 20
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#define HSPHY_FW_VERSION_HOTFIX_MASK 0xF0000
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#define HSPHY_FW_VERSION_HOTFIX_OFFSET 16
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#define HSPHY_FW_VERSION_BUILD_MASK 0xF000
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#define HSPHY_FW_VERSION_BUILD_OFFSET 12
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#define HSPHY_FW_VERSION_EV_BITPROG_MAJOR_MASK 0xF00
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#define HSPHY_FW_VERSION_EV_BITPROG_MAJOR_OFFSET 8
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#define HSPHY_FW_VERSION_EV_BITPROG_MINOR_MASK 0xFF
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#define HSPHY_FW_VERSION_EV_BITPROG_MINOR_OFFSET 0
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struct ip_push_model {
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uint16_t count;
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uint16_t address;
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uint32_t data[0];
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}__packed;
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static int heci_get_hsphy_payload(void *buf, uint32_t *buf_size, uint8_t *hash_buf,
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uint8_t *hash_alg, uint32_t *status)
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{
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size_t reply_size;
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struct heci_ip_load_request {
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struct mkhi_hdr hdr;
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uint32_t version;
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uint32_t operation;
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uint32_t dram_base_low;
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uint32_t dram_base_high;
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uint32_t memory_size;
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uint32_t reserved;
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} __packed msg = {
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.hdr = {
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.group_id = MKHI_GROUP_ID_BUP_COMMON,
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.command = GET_IP_FIRMWARE_CMD,
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},
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.version = 1,
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.operation = 1,
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.dram_base_low = (uintptr_t)buf,
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.dram_base_high = 0,
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.memory_size = *buf_size,
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.reserved = 0,
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};
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struct heci_ip_load_response {
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struct mkhi_hdr hdr;
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uint32_t payload_size;
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uint32_t reserved[2];
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uint32_t status;
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uint8_t hash_type;
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uint8_t hash[MAX_HASH_SIZE];
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} __packed reply;
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if (!buf || !buf_size || !hash_buf || !hash_alg) {
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printk(BIOS_ERR, "%s: Invalid parameters\n", __func__);
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return -1;
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}
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reply_size = sizeof(reply);
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memset(&reply, 0, reply_size);
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printk(BIOS_DEBUG, "HECI: Sending Get IP firmware command\n");
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if (heci_send_receive(&msg, sizeof(msg), &reply, &reply_size, HECI_MKHI_ADDR)) {
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printk(BIOS_ERR, "HECI: Get IP firmware failed\n");
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return -1;
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}
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if (reply.hdr.result) {
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printk(BIOS_ERR, "HECI: Get IP firmware response invalid\n");
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*status = reply.status;
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hexdump(&reply, sizeof(reply));
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return -1;
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}
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*buf_size = reply.payload_size;
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*hash_alg = reply.hash_type;
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*status = reply.status;
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memcpy(hash_buf, reply.hash, MAX_HASH_SIZE);
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printk(BIOS_DEBUG, "HECI: Get IP firmware success. Response:\n");
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printk(BIOS_DEBUG, " Payload size = 0x%x\n", *buf_size);
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printk(BIOS_DEBUG, " Hash type used for signing payload = 0x%x\n", *hash_alg);
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return 0;
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}
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static int verify_hsphy_hash(void *buf, uint32_t buf_size, uint8_t *hash_buf, uint8_t hash_alg)
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{
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enum vb2_hash_algorithm alg;
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uint32_t hash_size;
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uint8_t hash_calc[MAX_HASH_SIZE];
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switch (hash_alg) {
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case HASHALG_SHA256:
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alg = VB2_HASH_SHA256;
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hash_size = VB2_SHA256_DIGEST_SIZE;
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break;
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case HASHALG_SHA384:
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alg = VB2_HASH_SHA384;
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hash_size = VB2_SHA384_DIGEST_SIZE;
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break;
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case HASHALG_SHA512:
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alg = VB2_HASH_SHA512;
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hash_size = VB2_SHA512_DIGEST_SIZE;
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break;
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case HASHALG_SHA1:
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default:
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printk (BIOS_ERR, "Hash alg %d not supported, try SHA384\n", hash_alg);
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alg = VB2_HASH_SHA384;
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hash_size = VB2_SHA384_DIGEST_SIZE;
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break;
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}
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if (vb2_digest_buffer(buf, buf_size, alg, hash_calc, hash_size)) {
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printk(BIOS_ERR, "HSPHY SHA calculation failed\n");
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return -1;
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}
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if (memcmp(hash_buf, hash_calc, hash_size)) {
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printk(BIOS_ERR, "HSPHY SHA hashes do not match\n");
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hexdump(hash_buf, hash_size);
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hexdump(hash_calc, hash_size);
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return -1;
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}
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return 0;
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}
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static void upload_hsphy_to_cpu_pcie(void *buf, uint32_t buf_size)
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{
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uint32_t i = 0, j;
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struct ip_push_model *push_model = (struct ip_push_model *)buf;
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while (i < buf_size) {
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i += sizeof (*push_model);
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if ((push_model->address == 0) && (push_model->count == 0)) {
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break; // End of file
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}
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for (j = 0; j < push_model->count; j++) {
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REGBAR32(CPU_PID_PCIE_PHYX16_BROADCAST,
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push_model->address) = push_model->data[j];
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i += sizeof (uint32_t);
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}
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push_model = (struct ip_push_model *)(buf + i);
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}
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}
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static bool is_bios_hsphy_loader(void)
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{
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uint64_t cap = REGBAR64(CPU_PID_PCIE_BUTTRESSx16_0, HSPHY_MEM_IP_CAP_0);
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if ((cap >> HSPHY_MEM_IP_CAP_0_BIOS_LOADER) & HSPHY_MEM_IP_CAP_0_MASK) {
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printk(BIOS_DEBUG, "HSPHY: BIOS is the loader of HSPHY firmware\n");
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return true;
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}
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printk(BIOS_DEBUG, "HSPHY: BIOS is not the loader of HSPHY firmware\n");
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return false;
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}
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static void set_hsphy_verifier_error_code(uint8_t image_number, uint32_t error_code)
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{
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uint32_t error = REGBAR32(CPU_PID_PCIE_BUTTRESSx16_0, HSPHY_MEM_VERIFIER_ERROR_STATUS);
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error |= (error_code << HSPHY_MEM_VERIFIER_ERROR_STATUS_ERROR_CODE);
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error |= (1 << image_number);
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REGBAR32(CPU_PID_PCIE_BUTTRESSx16_0, HSPHY_MEM_VERIFIER_ERROR_STATUS) = error;
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}
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void load_and_init_hsphy(void)
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{
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void *hsphy_buf;
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uint8_t hsphy_hash[MAX_HASH_SIZE] = { 0 };
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uint8_t hash_type;
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uint32_t buf_size = HSPHY_PAYLOAD_SIZE;
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pci_devfn_t dev = PCH_DEV_CSE;
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uint16_t pci_cmd_bme_mem = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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uint32_t status;
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if (!is_devfn_enabled(SA_DEVFN_CPU_PCIE1_0) &&
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!is_devfn_enabled(SA_DEVFN_CPU_PCIE1_1)) {
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printk(BIOS_DEBUG, "All HSPHY ports disabled, skipping HSPHY loading\n");
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}
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if (!is_bios_hsphy_loader())
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return;
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/* Align the buffer to page size, otherwise the HECI command will fail */
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hsphy_buf = memalign(4*KiB, HSPHY_PAYLOAD_SIZE);
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if (!hsphy_buf) {
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printk(BIOS_ERR, "Could not allocate memory for HSPHY blob\n");
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return;
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}
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memset(hsphy_buf, 0, HSPHY_PAYLOAD_SIZE);
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if (!is_cse_enabled()) {
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printk(BIOS_ERR, "%s: CSME not enabled or not visible\n", __func__);
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return;
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}
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/* Ensure BAR, BME and memory space are enabled */
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if ((pci_read_config16(dev, PCI_COMMAND) & pci_cmd_bme_mem) != pci_cmd_bme_mem)
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pci_or_config16(dev, PCI_COMMAND, pci_cmd_bme_mem);
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if (pci_read_config32(dev, PCI_BASE_ADDRESS_0) == 0) {
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pci_and_config16(dev, PCI_COMMAND, ~pci_cmd_bme_mem);
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, HECI1_BASE_ADDRESS);
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pci_or_config16(dev, PCI_COMMAND, pci_cmd_bme_mem);
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}
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if (heci_get_hsphy_payload(hsphy_buf, &buf_size, hsphy_hash, &hash_type, &status)) {
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set_hsphy_verifier_error_code(1, status);
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return;
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}
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if (verify_hsphy_hash(hsphy_buf, buf_size, hsphy_hash, hash_type))
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return;
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upload_hsphy_to_cpu_pcie(hsphy_buf, buf_size);
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free(hsphy_buf);
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}
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static bool is_hsphy_fw_download_complete(uint32_t cpu_pcie_dev)
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{
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uint16_t pid;
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switch (cpu_pcie_dev) {
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case SA_DEVFN_CPU_PCIE1_0:
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pid = CPU_PID_PCIE_PHYx16_0;
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break;
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case SA_DEVFN_CPU_PCIE1_1:
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pid = CPU_PID_PCIE_PHYx16_1;
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break;
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default:
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printk(BIOS_ERR, "%s: incorrect CPU PCIe devfn\n", __func__);
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return false;
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}
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return (REGBAR32(pid, HSPHY_RECIPE_VERSION) == 0) ? false : true;
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}
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void print_hsphy_version(uint32_t cpu_pcie_dev)
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{
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uint32_t hsphy_ver, hsphy_recipe;
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if (!is_hsphy_fw_download_complete(cpu_pcie_dev)) {
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printk(BIOS_ERR, "%s: HSPHY firmware download not complete\n", __func__);
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return;
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}
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switch (cpu_pcie_dev) {
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case SA_DEVFN_CPU_PCIE1_0:
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printk(BIOS_DEBUG, "Printing HSPHY version for CPU PCIe 0:1.0\n");
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hsphy_ver = REGBAR32(CPU_PID_PCIE_PHYx16_0, HSPHY_FW_VERSION);;
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hsphy_recipe = REGBAR32(CPU_PID_PCIE_PHYx16_0, HSPHY_RECIPE_VERSION);
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break;
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case SA_DEVFN_CPU_PCIE1_1:
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printk(BIOS_DEBUG, "Printing HSPHY version for CPU PCIe 0:1.1\n");
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hsphy_ver = REGBAR32(CPU_PID_PCIE_PHYx16_1, HSPHY_FW_VERSION);;
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hsphy_recipe = REGBAR32(CPU_PID_PCIE_PHYx16_1, HSPHY_RECIPE_VERSION);
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break;
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default:
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printk(BIOS_ERR, "%s: incorrect CPU PCIe devfn\n", __func__);
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return;
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}
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printk(BIOS_DEBUG, "HSPHY: Recipe version: %d.%d\n",
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(hsphy_recipe & HSPHY_RECIPE_VERSION_MAJOR_MASK) >>
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HSPHY_RECIPE_VERSION_MAJOR_OFFSET,
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(hsphy_recipe & HSPHY_RECIPE_VERSION_MINOR_MASK) >>
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HSPHY_RECIPE_VERSION_MINOR_OFFSET);
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printk(BIOS_DEBUG, "HSPHY: Firmware version: %d.%d.%d.%d.%d.%d\n",
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(hsphy_ver & HSPHY_FW_VERSION_PROD_MAJOR_MASK) >>
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HSPHY_FW_VERSION_PROD_MAJOR_OFFSET,
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(hsphy_ver & HSPHY_FW_VERSION_PROD_MINOR_MASK) >>
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HSPHY_FW_VERSION_PROD_MAJOR_OFFSET,
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(hsphy_ver & HSPHY_FW_VERSION_HOTFIX_MASK) >>
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HSPHY_FW_VERSION_HOTFIX_OFFSET,
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(hsphy_ver & HSPHY_FW_VERSION_BUILD_MASK) >>
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HSPHY_FW_VERSION_BUILD_OFFSET,
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(hsphy_ver & HSPHY_FW_VERSION_EV_BITPROG_MAJOR_MASK) >>
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HSPHY_FW_VERSION_EV_BITPROG_MAJOR_OFFSET,
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(hsphy_ver & HSPHY_FW_VERSION_EV_BITPROG_MINOR_MASK) >>
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HSPHY_FW_VERSION_EV_BITPROG_MINOR_OFFSET);
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}
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9
src/soc/intel/alderlake/include/soc/hsphy.h
Normal file
9
src/soc/intel/alderlake/include/soc/hsphy.h
Normal file
@@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_ALDERLAKE_HSPHY_H_
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#define _SOC_ALDERLAKE_HSPHY_H_
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void load_and_init_hsphy(void);
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void print_hsphy_version(uint32_t cpu_pcie_dev);
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#endif /* _SOC_ALDERLAKE_HSPHY_H_ */
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