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soc/intel/{tgl,adl}/acpi: Unify the way D3Cold is enabled

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Both Alder Lake and Tiger Lake have Kconfig options for S3, which
disables support for D3Cold. Unify these so that they are easier
to compare.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72798
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes
2023-02-06 09:09:16 +00:00
committed by Lean Sheng Tan
parent 699f0d48ad
commit 6b5b7e0654
8 changed files with 178 additions and 184 deletions
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2
src/soc/intel/alderlake/acpi/tcss.asl
View File

@@ -654,7 +654,7 @@ Scope (\_SB.PCI0)
STAT = 0
}
}
#endif
#endif // SOC_INTEL_ALDERLAKE_S3
/*
* TCSS xHCI device

6
src/soc/intel/alderlake/acpi/tcss_dma.asl
View File

@@ -32,7 +32,7 @@ Method (_S0W, 0x0)
Return (0x04)
#else
Return (0x03)
#endif
#endif // SOC_INTEL_ALDERLAKE_S3
}
Method (_PR0)
@@ -49,7 +49,7 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif
#endif // SOC_INTEL_ALDERLAKE_S3
}
Method (_PR3)
@@ -66,7 +66,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif
#endif // SOC_INTEL_ALDERLAKE_S3
}
/*

6
src/soc/intel/alderlake/acpi/tcss_pcierp.asl
View File

@@ -251,7 +251,7 @@ Method (_S0W, 0x0, NotSerialized)
Return (0x4)
#else
Return (0x3)
#endif
#endif // SOC_INTEL_ALDERLAKE_S3
}
Method (_PR0)
@@ -268,7 +268,7 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif
#endif // SOC_INTEL_ALDERLAKE_S3
}
Method (_PR3)
@@ -285,7 +285,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif
#endif // SOC_INTEL_ALDERLAKE_S3
}
/*

4
src/soc/intel/alderlake/acpi/tcss_xhci.asl
View File

@@ -34,7 +34,7 @@ Method (_S0W, 0x0, NotSerialized)
Return (0x4)
#else
Return (0x3)
#endif
#endif // SOC_INTEL_ALDERLAKE_S3
}
/*
@@ -53,7 +53,7 @@ Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
#endif
#endif // SOC_INTEL_ALDERLAKE_S3
/*
* XHCI controller _DSM method

206
src/soc/intel/tigerlake/acpi/tcss.asl
View File

@@ -42,12 +42,6 @@
Scope (\_SB)
{
#if CONFIG(SOC_INTEL_TIGERLAKE_S3)
Name (S0IX, 0)
#else
Name (S0IX, 1)
#endif
/* Device base address */
Method (BASE, 1)
{
@@ -682,118 +676,118 @@ Scope (\_SB.PCI0)
}
}
If (S0IX == 1) {
Method (TCON, 0)
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Method (TCON, 0)
{
/* Reset IOM D3 cold bit if it is in D3 cold now. */
If (TD3C == 1) /* It was in D3 cold before. */
{
/* Reset IOM D3 cold bit if it is in D3 cold now. */
If (TD3C == 1) /* It was in D3 cold before. */
{
/* Reset IOM D3 cold bit. */
TD3C = 0 /* Request IOM for D3 cold exit sequence. */
Local0 = 0 /* Time check counter variable */
/* Wait for ack, the maximum wait time for the ack is 100 msec. */
While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) {
/*
* Wait in this loop until TACK becomes 0 with timeout
* TCSS_IOM_ACK_TIMEOUT_IN_MS by default.
*/
Sleep (1) /* Delay of 1ms. */
Local0++
}
/* Reset IOM D3 cold bit. */
TD3C = 0 /* Request IOM for D3 cold exit sequence. */
Local0 = 0 /* Time check counter variable */
/* Wait for ack, the maximum wait time for the ack is 100 msec. */
While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) {
/*
* Wait in this loop until TACK becomes 0 with timeout
* TCSS_IOM_ACK_TIMEOUT_IN_MS by default.
*/
Sleep (1) /* Delay of 1ms. */
Local0++
}
If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) {
Printf("Error: Timeout occurred.")
}
Else
{
/*
* Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and
* acknowledgement by IOM.
*/
TCD3 = 0
/*
* If the TCSS Deven is cleared by BIOS Mailbox request, then
* restore to previously saved value of TCSS DEVNE.
*/
Local0 = 0
While (\_SB.PCI0.TXHC.VDID == 0xFFFFFFFF) {
If (DSGS () == 1) {
DSCR (0)
}
Local0++
If (Local0 == 5) {
Printf("pCode mailbox command failed.")
Break
}
If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) {
Printf("Error: Timeout occurred.")
}
Else
{
/*
* Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and
* acknowledgement by IOM.
*/
TCD3 = 0
/*
* If the TCSS Deven is cleared by BIOS Mailbox request, then
* restore to previously saved value of TCSS DEVNE.
*/
Local0 = 0
While (\_SB.PCI0.TXHC.VDID == 0xFFFFFFFF) {
If (DSGS () == 1) {
DSCR (0)
}
Local0++
If (Local0 == 5) {
Printf("pCode mailbox command failed.")
Break
}
}
}
Else {
Printf("Drop TCON due to it is already exit D3 cold.")
}
}
Else {
Printf("Drop TCON due to it is already exit D3 cold.")
}
}
Method (TCOF, 0)
Method (TCOF, 0)
{
If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0)
|| (\_SB.PCI0.TDM1.SD3C != 0))
{
If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0)
|| (\_SB.PCI0.TDM1.SD3C != 0))
{
Printf("Skip D3C entry.")
Return
}
/*
* If the TCSS Deven in normal state, then Save current TCSS DEVEN value and
* clear it.
*/
Local0 = 0
While (\_SB.PCI0.TXHC.VDID != 0xFFFFFFFF) {
If (DSGS () == 0) {
DSCR (1)
}
Local0++
If (Local0 == 5) {
Printf("pCode mailbox command failed.")
Break
}
}
/*
* Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold.
*/
TCD3 = 1
/* Request IOM for D3 cold entry sequence. */
TD3C = 1
Printf("Skip D3C entry.")
Return
}
PowerResource (D3C, 5, 0)
/*
* If the TCSS Deven in normal state, then Save current TCSS DEVEN value and
* clear it.
*/
Local0 = 0
While (\_SB.PCI0.TXHC.VDID != 0xFFFFFFFF) {
If (DSGS () == 0) {
DSCR (1)
}
Local0++
If (Local0 == 5) {
Printf("pCode mailbox command failed.")
Break
}
}
/*
* Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold.
*/
TCD3 = 1
/* Request IOM for D3 cold entry sequence. */
TD3C = 1
}
PowerResource (D3C, 5, 0)
{
/*
* Variable to save power state
* 1 - TC Cold request cleared.
* 0 - TC Cold request sent.
*/
Name (STAT, 0x1)
Method (_STA, 0)
{
/*
* Variable to save power state
* 1 - TC Cold request cleared.
* 0 - TC Cold request sent.
*/
Name (STAT, 0x1)
Method (_STA, 0)
{
Return (STAT)
}
Method (_ON, 0)
{
\_SB.PCI0.TCON()
STAT = 1
}
Method (_OFF, 0)
{
\_SB.PCI0.TCOF()
STAT = 0
}
Return (STAT)
}
} /* End: S0IX */
Method (_ON, 0)
{
\_SB.PCI0.TCON()
STAT = 1
}
Method (_OFF, 0)
{
\_SB.PCI0.TCOF()
STAT = 0
}
}
#endif // SOC_INTEL_TIGERLAKE_S3
/*
* TCSS xHCI device

54
src/soc/intel/tigerlake/acpi/tcss_dma.asl
View File

@@ -27,11 +27,11 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0)
{
If (S0IX == 1) {
Return (0x04)
} Else {
Return (0x03)
}
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Return (0x04)
#else
Return (0x03)
#endif // SOC_INTEL_TIGERLAKE_S3
}
/*
@@ -40,36 +40,36 @@ Method (_S0W, 0x0)
*/
Method (_PR0)
{
If (S0IX == 1) {
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
If (DUID == 0) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#else
If (DUID == 0) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_TIGERLAKE_S3
}
Method (_PR3)
{
If (S0IX == 1) {
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
If (DUID == 0) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#else
If (DUID == 0) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_TIGERLAKE_S3
}
/*

54
src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
View File

@@ -247,45 +247,45 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
If (S0IX == 1) {
Return (0x4)
} Else {
Return (0x3)
}
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Return (0x4)
#else
Return (0x3)
#endif // SOC_INTEL_ALDERLAKE_S3
}
Method (_PR0)
{
If (S0IX == 1) {
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#else
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_TIGERLAKE_S3
}
Method (_PR3)
{
If (S0IX == 1) {
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#else
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_TIGERLAKE_S3
}
/*

30
src/soc/intel/tigerlake/acpi/tcss_xhci.asl
View File

@@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
If (S0IX == 1) {
Return (0x4)
} Else {
Return (0x3)
}
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Return (0x4)
#else
Return (0x3)
#endif // SOC_INTEL_TIGERLAKE_S3
}
/*
@@ -43,18 +43,18 @@ Method (_S0W, 0x0, NotSerialized)
*/
Name (SD3C, 0)
If (S0IX == 1) {
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
}
Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
}
Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
#endif // SOC_INTEL_TIGERLAKE_S3
/*
* XHCI controller _DSM method
*/