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soc/intel/{tgl,adl}/acpi: Unify the way D3Cold is enabled

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Both Alder Lake and Tiger Lake have Kconfig options for S3, which
disables support for D3Cold. Unify these so that they are easier
to compare.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72798
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes
2023-02-06 09:09:16 +00:00
committed by Lean Sheng Tan
parent 699f0d48ad
commit 6b5b7e0654
8 changed files with 178 additions and 184 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/alderlake/acpi/tcss.asl
View File

@@ -654,7 +654,7 @@ Scope (\_SB.PCI0)
STAT = 0 STAT = 0
} }
} }
#endif #endif // SOC_INTEL_ALDERLAKE_S3
/* /*
* TCSS xHCI device * TCSS xHCI device

6
src/soc/intel/alderlake/acpi/tcss_dma.asl
View File

@@ -32,7 +32,7 @@ Method (_S0W, 0x0)
Return (0x04) Return (0x04)
#else #else
Return (0x03) Return (0x03)
#endif #endif // SOC_INTEL_ALDERLAKE_S3
} }
Method (_PR0) Method (_PR0)
@@ -49,7 +49,7 @@ Method (_PR0)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif #endif // SOC_INTEL_ALDERLAKE_S3
} }
Method (_PR3) Method (_PR3)
@@ -66,7 +66,7 @@ Method (_PR3)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif #endif // SOC_INTEL_ALDERLAKE_S3
} }
/* /*

6
src/soc/intel/alderlake/acpi/tcss_pcierp.asl
View File

@@ -251,7 +251,7 @@ Method (_S0W, 0x0, NotSerialized)
Return (0x4) Return (0x4)
#else #else
Return (0x3) Return (0x3)
#endif #endif // SOC_INTEL_ALDERLAKE_S3
} }
Method (_PR0) Method (_PR0)
@@ -268,7 +268,7 @@ Method (_PR0)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif #endif // SOC_INTEL_ALDERLAKE_S3
} }
Method (_PR3) Method (_PR3)
@@ -285,7 +285,7 @@ Method (_PR3)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif #endif // SOC_INTEL_ALDERLAKE_S3
} }
/* /*

4
src/soc/intel/alderlake/acpi/tcss_xhci.asl
View File

@@ -34,7 +34,7 @@ Method (_S0W, 0x0, NotSerialized)
Return (0x4) Return (0x4)
#else #else
Return (0x3) Return (0x3)
#endif #endif // SOC_INTEL_ALDERLAKE_S3
} }
/* /*
@@ -53,7 +53,7 @@ Method (_PR3)
{ {
Return (Package () { \_SB.PCI0.D3C }) Return (Package () { \_SB.PCI0.D3C })
} }
#endif #endif // SOC_INTEL_ALDERLAKE_S3
/* /*
* XHCI controller _DSM method * XHCI controller _DSM method

10
src/soc/intel/tigerlake/acpi/tcss.asl
View File

@@ -42,12 +42,6 @@
Scope (\_SB) Scope (\_SB)
{ {
#if CONFIG(SOC_INTEL_TIGERLAKE_S3)
Name (S0IX, 0)
#else
Name (S0IX, 1)
#endif
/* Device base address */ /* Device base address */
Method (BASE, 1) Method (BASE, 1)
{ {
@@ -682,7 +676,7 @@ Scope (\_SB.PCI0)
} }
} }
If (S0IX == 1) { #if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Method (TCON, 0) Method (TCON, 0)
{ {
/* Reset IOM D3 cold bit if it is in D3 cold now. */ /* Reset IOM D3 cold bit if it is in D3 cold now. */
@@ -793,7 +787,7 @@ Scope (\_SB.PCI0)
STAT = 0 STAT = 0
} }
} }
} /* End: S0IX */ #endif // SOC_INTEL_TIGERLAKE_S3
/* /*
* TCSS xHCI device * TCSS xHCI device

18
src/soc/intel/tigerlake/acpi/tcss_dma.asl
View File

@@ -27,11 +27,11 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0) Method (_S0W, 0x0)
{ {
If (S0IX == 1) { #if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Return (0x04) Return (0x04)
} Else { #else
Return (0x03) Return (0x03)
} #endif // SOC_INTEL_TIGERLAKE_S3
} }
/* /*
@@ -40,36 +40,36 @@ Method (_S0W, 0x0)
*/ */
Method (_PR0) Method (_PR0)
{ {
If (S0IX == 1) { #if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If (DUID == 0) { If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
} }
} Else { #else
If (DUID == 0) { If (DUID == 0) {
Return (Package() { \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.TBT0 })
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
} #endif // SOC_INTEL_TIGERLAKE_S3
} }
Method (_PR3) Method (_PR3)
{ {
If (S0IX == 1) { #if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If (DUID == 0) { If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
} }
} Else { #else
If (DUID == 0) { If (DUID == 0) {
Return (Package() { \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.TBT0 })
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
} #endif // SOC_INTEL_TIGERLAKE_S3
} }
/* /*

18
src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
View File

@@ -247,45 +247,45 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized) Method (_S0W, 0x0, NotSerialized)
{ {
If (S0IX == 1) { #if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Return (0x4) Return (0x4)
} Else { #else
Return (0x3) Return (0x3)
} #endif // SOC_INTEL_ALDERLAKE_S3
} }
Method (_PR0) Method (_PR0)
{ {
If (S0IX == 1) { #if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If ((TUID == 0) || (TUID == 1)) { If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
} }
} Else { #else
If ((TUID == 0) || (TUID == 1)) { If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.TBT0 })
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
} #endif // SOC_INTEL_TIGERLAKE_S3
} }
Method (_PR3) Method (_PR3)
{ {
If (S0IX == 1) { #if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
If ((TUID == 0) || (TUID == 1)) { If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else { } Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
} }
} Else { #else
If ((TUID == 0) || (TUID == 1)) { If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.TBT0 }) Return (Package() { \_SB.PCI0.TBT0 })
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
} #endif // SOC_INTEL_TIGERLAKE_S3
} }
/* /*

10
src/soc/intel/tigerlake/acpi/tcss_xhci.asl
View File

@@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized) Method (_S0W, 0x0, NotSerialized)
{ {
If (S0IX == 1) { #if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Return (0x4) Return (0x4)
} Else { #else
Return (0x3) Return (0x3)
} #endif // SOC_INTEL_TIGERLAKE_S3
} }
/* /*
@@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/ */
Name (SD3C, 0) Name (SD3C, 0)
If (S0IX == 1) { #if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
Method (_PR0) Method (_PR0)
{ {
Return (Package () { \_SB.PCI0.D3C }) Return (Package () { \_SB.PCI0.D3C })
@@ -53,7 +53,7 @@ If (S0IX == 1) {
{ {
Return (Package () { \_SB.PCI0.D3C }) Return (Package () { \_SB.PCI0.D3C })
} }
} #endif // SOC_INTEL_TIGERLAKE_S3
/* /*
* XHCI controller _DSM method * XHCI controller _DSM method