mb/intel/kblrvp: Enable Kabylake RVP8
Add support for KBL RVP8 board * Add KBL RVP8 support in Konfig. * Add KBL RVP8 config option in make menuconfig. * Add descriptor and ME binary paths for RVP8 in Kconfig. * Add RVP8 board name Kconfig.name. * Add devicetree.cb for RVP8 in the variants path. * Add gpio.h for RVP8 in variants/include/variant path. TEST= Build and boot RVP8. Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23383 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
V Sowmya
Martin Roth
@@ -1,4 +1,4 @@
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if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7
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if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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@@ -8,8 +8,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_SMI_HANDLER
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7
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select SOC_INTEL_SKYLAKE
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select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8
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select MAINBOARD_USES_FSP2_0
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select MAINBOARD_HAS_CHROMEOS
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select GENERIC_SPD_BIN
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@@ -52,6 +53,7 @@ config VARIANT_DIR
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string
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default "rvp3" if BOARD_INTEL_KBLRVP3
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default "rvp7" if BOARD_INTEL_KBLRVP7
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default "rvp8" if BOARD_INTEL_KBLRVP8
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config MAINBOARD_PART_NUMBER
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string
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@@ -83,12 +85,14 @@ config IFD_BIN_PATH
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depends on HAVE_IFD_BIN
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default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp3.bin" if BOARD_INTEL_KBLRVP3
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default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp7.bin" if BOARD_INTEL_KBLRVP7
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default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp8.bin" if BOARD_INTEL_KBLRVP8
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config ME_BIN_PATH
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string
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depends on HAVE_ME_BIN
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default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp3.bin" if BOARD_INTEL_KBLRVP3
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default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp7.bin" if BOARD_INTEL_KBLRVP7
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default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp8.bin" if BOARD_INTEL_KBLRVP8
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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@@ -2,3 +2,5 @@ config BOARD_INTEL_KBLRVP3
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bool "Kabylake LPDDR3 RVP3"
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config BOARD_INTEL_KBLRVP7
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bool "Kabylake DDR3L RVP7"
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config BOARD_INTEL_KBLRVP8
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bool "Kabylake DDR4 RVP8"
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@@ -14,4 +14,6 @@
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* GNU General Public License for more details.
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*/
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#if !IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)
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#include "variant/hda_verb.h"
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#endif
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@@ -49,6 +49,9 @@ int mainboard_io_trap_handler(int smif)
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void mainboard_smi_gpi_handler(const struct gpi_status *sts)
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{
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if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))
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return;
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if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
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if (gpi_status_get(sts, EC_SMI_GPI))
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chromeec_smi_process_events();
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272
src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
Normal file
272
src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
Normal file
@@ -0,0 +1,272 @@
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chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "0"
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register "deep_s5_enable_dc" = "0"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable DPTF
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register "dptf_enable" = "1"
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# FSP Configuration
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register "SmbusEnable" = "1"
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register "ScsEmmcEnabled" = "0"
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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register "SaGv" = "3"
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register "PmTimerDisabled" = "0"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
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# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
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register "PmConfigSlpS3MinAssert" = "0x02"
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# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
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register "PmConfigSlpS4MinAssert" = "0x04"
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# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
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register "PmConfigSlpSusMinAssert" = "0x03"
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# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
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register "PmConfigSlpAMinAssert" = "0x03"
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# Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
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register "SerialIrqConfigSirqEnable" = "0x01"
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register "SerialIrqConfigSirqMode" = "0x01"
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# VR Settings Configuration for 5 Domains
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------------+-------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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.psi2threshold = 0x10, \
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.psi3threshold = 0x4, \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0, \
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.voltage_limit = 0x0 \
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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.psi2threshold = 0x14, \
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.psi3threshold = 0x4, \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0, \
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.voltage_limit = 0x0 \
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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.psi2threshold = 0x14, \
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.psi3threshold = 0x4, \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0 ,\
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.voltage_limit = 0x0 \
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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.psi2threshold = 0x14, \
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.psi3threshold = 0x4, \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0, \
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.voltage_limit = 0x0 \
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}"
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register "FspSkipMpInit" = "1"
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# Enable Root port.
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[4]" = "1"
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register "PcieRpEnable[8]" = "1"
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register "PcieRpEnable[16]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[3]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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register "PcieRpClkReqSupport[8]" = "1"
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register "PcieRpClkReqSupport[16]" = "1"
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# SRCCLKREQ#
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register "PcieRpClkReqNumber[3]" = "2"
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register "PcieRpClkReqNumber[4]" = "1"
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register "PcieRpClkReqNumber[8]" = "6"
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register "PcieRpClkReqNumber[16]" = "7"
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register "usb2_ports[0]" = "USB2_PORT_MAX(OC2)" # Type-C Port
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register "usb2_ports[1]" = "USB2_PORT_MAX(OC5)" # Front panel
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register "usb2_ports[2]" = "USB2_PORT_MAX(OC4)" # Back panel
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register "usb2_ports[3]" = "USB2_PORT_MAX(OC4)" # Back panel
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register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Back panel-1
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register "usb2_ports[5]" = "USB2_PORT_MAX(OC1)" # Back panel
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register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel
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register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # Front panel
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register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # M.2 BT
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register "usb2_ports[9]" = "USB2_PORT_MAX(OC2)" # Front panel
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register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel
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register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel-1
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register "usb2_ports[12]" = "USB2_PORT_MAX(OC3)" # Back panel
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register "usb2_ports[13]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Back panel
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Back panel
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # Back panel-2
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Front Panel
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register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel
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register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel
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register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC3)" # Back panel
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register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LAN
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register "SsicPortEnable" = "1" # Enable SSIC for WWAN
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register "EnableSata" = "1"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable" = "{ \
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[0] = 1, \
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[1] = 1, \
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[2] = 1, \
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[3] = 1, \
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[4] = 1, \
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[5] = 1, \
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[6] = 1, \
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[7] = 1, \
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}"
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{ \
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[PchSerialIoIndexI2C0] = PchSerialIoPci, \
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[PchSerialIoIndexI2C1] = PchSerialIoPci, \
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
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[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart0] = PchSerialIoPci, \
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[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \
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}"
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# PL2 override 25W
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register "tdp_pl2_override" = "25"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# Enable/Disable VMX feature
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register "VmxEnable" = "0"
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# Use default SD card detect GPIO configuration
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#register "sdcard_cd_gpio_default" = "GPP_D10"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 on end # I2C #2
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device pci 15.3 on end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on end # SATA
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device pci 19.0 on end # UART #2
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device pci 19.1 on end # I2C #5
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device pci 19.2 on end # I2C #4
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 on end # PCI Express Port 3
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device pci 1c.3 on end # PCI Express Port 4
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device pci 1c.4 on end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1e.0 on end # UART #0
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device pci 1e.1 on end # UART #1
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device pci 1e.2 on end # GSPI #0
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device pci 1e.3 on end # GSPI #1
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device pci 1e.4 off end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.6 on end # SDCard
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device pci 1f.0 on
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#chip drivers/pc80/tpm
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# device pnp 0c31.0 on end
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#end
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end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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||||
device pci 1f.5 on end # PCH SPI
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device pci 1f.6 on end # GbE
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end
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||||
end
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183
src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h
Normal file
183
src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h
Normal file
@@ -0,0 +1,183 @@
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/*
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||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
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*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _GPIORVP8_H
|
||||
#define _GPIORVP8_H
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||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* TCA6424A I/O Expander */
|
||||
#define IO_EXPANDER_BUS 4
|
||||
#define IO_EXPANDER_0_ADDR 0x22
|
||||
#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */
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||||
#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */
|
||||
#define IO_EXPANDER_P1CONF 0x0D
|
||||
#define IO_EXPANDER_P1DOUT 0x05
|
||||
#define IO_EXPANDER_P2CONF 0x0E
|
||||
#define IO_EXPANDER_P2DOUT 0x06
|
||||
#define IO_EXPANDER_1_ADDR 0x23
|
||||
|
||||
/* GPE_EC_WAKE */
|
||||
#define GPE_EC_WAKE GPE0_LAN_WAK
|
||||
#define EC_SMI_GPI GPP_I3
|
||||
|
||||
/*
|
||||
* Gpio based irq for touchpad, 18th index in North Bank
|
||||
* MAX_DIRECT_IRQ + GPSW_SIZE + 19
|
||||
*/
|
||||
#define KBLRVP_TOUCHPAD_IRQ 33
|
||||
|
||||
#define KBLRVP_TOUCH_IRQ 31
|
||||
|
||||
#define BOARD_TOUCHPAD_NAME "touchpad"
|
||||
#define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ
|
||||
#define BOARD_TOUCHPAD_I2C_BUS 0
|
||||
#define BOARD_TOUCHPAD_I2C_ADDR 0x20
|
||||
|
||||
#define BOARD_TOUCHSCREEN_NAME "touchscreen"
|
||||
#define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ
|
||||
#define BOARD_TOUCHSCREEN_I2C_BUS 0
|
||||
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3),
|
||||
/* EC_LPC_IO0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3),
|
||||
/* EC_LPC_IO1*/ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3),
|
||||
/* EC_LPC_IO2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3),
|
||||
/* EC_LPC_IO3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3),
|
||||
/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF3),
|
||||
/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3),
|
||||
/* PIRQAB */ PAD_CFG_GPI(GPP_A7, NONE, DEEP),
|
||||
/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
|
||||
/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
|
||||
/* PMEB */ PAD_CFG_GPI(GPP_A11, NONE, DEEP),
|
||||
/* SUS_PWR_ACK_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
/* PM_SUS_ESPI_RST */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3),
|
||||
/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1),
|
||||
/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B3, 1, DEEP),
|
||||
/* EXTTS_SNI_DRV1 */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1),
|
||||
/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES),
|
||||
/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1),
|
||||
/* GSPI0_MISO */ PAD_CFG_GPO(GPP_B17, 1, DEEP),
|
||||
/* PCHHOTB */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2),
|
||||
/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP),
|
||||
/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
/* SML0_DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
/* SML1_DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
|
||||
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
|
||||
/* UART0_RTS_N */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
|
||||
/* UART0_CTS_N */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
|
||||
/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
/* UART2_RTS_N */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
|
||||
/* UART2_CTS_N */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
|
||||
/* SSP0_SFRM */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
/* SSP0_TXD */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
/* SSP0_RXD */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
/* SSP0_SCLK */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
/* SATAE_IFDET */ PAD_CFG_NF(GPP_E0, 20K_PU, DEEP, NF1),
|
||||
/* SATAE_IFDET */ PAD_CFG_NF(GPP_E1, 20K_PU, DEEP, NF1),
|
||||
/* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
|
||||
/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
|
||||
/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
|
||||
/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
|
||||
/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
|
||||
/* SATAXPCIE_4 */ PAD_CFG_NF(GPP_F1, 20K_PU, DEEP,NF1),
|
||||
/* SATA_DEVSLP_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, YES),
|
||||
/* SATA_DEVSLP_4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
/* SATA_SCLOCK */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP),
|
||||
/* SATA_SLOAD */ PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
/* SATA_SDATAOUT1 */ PAD_CFG_GPI_APIC(GPP_F12, NONE, DEEP),
|
||||
/* SATA_SDATAOUT0 */ PAD_CFG_GPI_APIC(GPP_F13, NONE, DEEP),
|
||||
/* H_SKTOCC_N */ PAD_CFG_GPI_APIC(GPP_F14, NONE, DEEP),
|
||||
/* USB_OC4_R_N */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||
/* USB_OC5_R_N */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||
/* USB_OC6_R_N */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||
/* USB_OC7_R_N */ PAD_CFG_GPO(GPP_F18, 1, DEEP),
|
||||
/* GPIO_PEG_RESET */ PAD_CFG_GPO(GPP_F22, 1, DEEP),
|
||||
/* VCORE_VBOOST_CTRL */ PAD_CFG_GPO(GPP_F23, 0, DEEP),
|
||||
/* FAN_TACH_0 */ PAD_CFG_GPO(GPP_G0, 1, DEEP),
|
||||
/* FAN_TACH_1 */ PAD_CFG_GPO(GPP_G1, 1, DEEP),
|
||||
/* FAN_TACH_2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES),
|
||||
/* FAN_TACH_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES),
|
||||
/* FAN_TACH_4 */ PAD_CFG_GPO(GPP_G4, 1, DEEP),
|
||||
/* FAN_TACH_5 */ PAD_CFG_GPI_APIC(GPP_G5, NONE, DEEP),
|
||||
/* FAN_TACH_6 */ PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, DEEP, YES),
|
||||
/* FAN_TACH_7 */ PAD_CFG_GPO(GPP_G7, 1, DEEP),
|
||||
/* GSXDOUT */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES),
|
||||
/* GSXSLOAD */ PAD_CFG_GPO(GPP_G13, 1, DEEP),
|
||||
/* GSXDIN */ PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, DEEP, YES),
|
||||
/* GSXSRESETB */ PAD_CFG_GPO(GPP_G15, 0, DEEP),
|
||||
/* GSXCLK */ PAD_CFG_GPO(GPP_G16, 0, DEEP),
|
||||
/* NMIB */ PAD_CFG_GPI_APIC(GPP_G18, NONE, DEEP),
|
||||
/* SMIB */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1),
|
||||
/* TEST_SETUP_MENU */ PAD_CFG_GPI_APIC(GPP_G20, NONE, DEEP),
|
||||
/* P_INTF_N */ PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES),
|
||||
/* PCH_PEGSLOT1 */ PAD_CFG_GPO(GPP_G22, 1, DEEP),
|
||||
/* IVCAM_DFU_R */ PAD_CFG_GPO(GPP_G23, 1, DEEP),
|
||||
/* SRCCLKREQB_8 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
/* SML2CLK */ PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
/* SML2DATA */ PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
/* SML3CLK */ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP),
|
||||
/* SML3DATA */ PAD_CFG_GPI_APIC(GPP_H14, NONE, DEEP),
|
||||
/* SML3ALERTB */ PAD_CFG_GPI_APIC(GPP_H15, NONE, DEEP),
|
||||
/* SML4DATA */ PAD_CFG_GPO(GPP_H17, 1, DEEP),
|
||||
/* LED_DRIVE */ PAD_CFG_GPO(GPP_H23, 0, DEEP),
|
||||
/* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
|
||||
/* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
|
||||
/* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
|
||||
/* DDSP_HPD_1 */ PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES),
|
||||
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, 20K_PD, DEEP, NF1),
|
||||
/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
|
||||
/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, 20K_PD, DEEP, NF1),
|
||||
/* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
|
||||
/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, 20K_PD, DEEP, NF1),
|
||||
/* EC_PCH_ACPRESENT */ PAD_CFG_GPO(GPD1, 0, DEEP),
|
||||
/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||
/* PM_PWRBTN_R_N */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
|
||||
/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* USB_WAKEOUT_N */ PAD_CFG_NF(GPD7, NONE, DEEP, NF1),
|
||||
/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
|
||||
};
|
||||
|
||||
/* Early pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
|
||||
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
Reference in New Issue
Block a user