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skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope

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Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
This commit is contained in:
Felix Singer 2024-06-23 00:25:18 +02:00
parent c7c8cf2edd
commit 6c83a71b0a
35 changed files with 672 additions and 564 deletions
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31
src/mainboard/51nb/x210/devicetree.cb
View File

@ -75,18 +75,6 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # mPCIe / WiFi Port
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # mSATA / WWAN Port
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
# PL1 override 25W
# PL2 override 44W
@ -101,7 +89,24 @@ chip soc/intel/skylake
device domain 0 on
device ref igpu on end
device ref sa_thermal on end
device ref south_xhci on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC1), // Type-A Port (left)
[1] = USB2_PORT_MID(OC1), // Type-A Port (left)
[2] = USB2_PORT_FLEX(OC_SKIP), // FPR
[3] = USB2_PORT_FLEX(OC_SKIP), // SD
[4] = USB2_PORT_FLEX(OC_SKIP), // INT
[5] = USB2_PORT_MID(OC1), // Type-A Port (right)
[6] = USB2_PORT_FLEX(OC_SKIP), // Webcam
[7] = USB2_PORT_MID(OC_SKIP), // mPCIe / WiFi Port
[8] = USB2_PORT_MID(OC_SKIP), // mSATA / WWAN Port
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC1), // Type-A Port (left)
[1] = USB3_PORT_DEFAULT(OC1), // Type-A Port (left)
}"
end
device ref thermal on end
device ref heci1 on end
device ref sata on end

33
src/mainboard/facebook/monolith/devicetree.cb
View File

@ -174,21 +174,6 @@ chip soc/intel/skylake
# Disable Aspm
register "pcie_rp_aspm[8]" = "AspmDisabled"
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 2 */
[1] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 1 */
[2] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 2 */
[3] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 1 */
[4] = USB2_PORT_SHORT(OC_SKIP), /* M2 Port */
[6] = USB2_PORT_SHORT(OC_SKIP), /* Audio board */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 2 */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 1 */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 2 */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
@ -209,7 +194,23 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref gmm on end
device ref south_xhci on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 2 */
[1] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 1 */
[2] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 2 */
[3] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 1 */
[4] = USB2_PORT_SHORT(OC_SKIP), /* M2 Port */
[6] = USB2_PORT_SHORT(OC_SKIP), /* Audio board */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 2 */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 1 */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 2 */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */
}"
end
device ref south_xdci on end
device ref thermal on end
device ref heci1 on end

21
src/mainboard/google/eve/devicetree.cb
View File

@ -141,15 +141,6 @@ chip soc/intel/skylake
#RP 5 uses CLK SRC 4
register "PcieRpClkSrcNumber[4]" = "4"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # H1
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@ -229,6 +220,18 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC0), // Type-C Port 1
[1] = USB2_PORT_FLEX(OC_SKIP), // Camera
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[4] = USB2_PORT_LONG(OC1), // Type-C Port 2
[6] = USB2_PORT_MID(OC_SKIP), // H1
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
}"
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"

35
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@ -233,22 +233,6 @@ chip soc/intel/skylake
# RP 12 uses CLK SRC 2
register "PcieRpClkSrcNumber[11]" = "2"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front
register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front
register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug
@ -306,6 +290,25 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC0), // Type-C
[1] = USB2_PORT_MID(OC3), // Type-A Rear
[2] = USB2_PORT_MID(OC2), // Type-A Front
[3] = USB2_PORT_MID(OC2), // Type-A Front
[4] = USB2_PORT_MID(OC1), // Type-A Rear
[5] = USB2_PORT_MID(OC1), // Type-A Rear
[6] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[7] = USB2_PORT_MID(OC_SKIP), // Type-A 2.0 / Debug
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C
[1] = USB3_PORT_DEFAULT(OC3), // Type-A Rear
[2] = USB3_PORT_DEFAULT(OC2), // Type-A Front
[3] = USB3_PORT_DEFAULT(OC2), // Type-A Front
[4] = USB3_PORT_DEFAULT(OC1), // Type-A Rear
[5] = USB3_PORT_DEFAULT(OC1), // Type-A Rear
}"
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"

31
src/mainboard/google/fizz/variants/endeavour/overridetree.cb
View File

@ -42,20 +42,6 @@ chip soc/intel/skylake
register "PcieRpEnable[10]" = "0"
register "PcieRpEnable[11]" = "0"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # HDMI
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Rear
register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Rear
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-A Rear
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # HDMI Audio
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # None
@ -78,6 +64,23 @@ chip soc/intel/skylake
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC_SKIP), // Type-C
[1] = USB2_PORT_MID(OC_SKIP), // HDMI
[2] = USB2_PORT_MID(OC2), // Type-A Rear
[3] = USB2_PORT_MID(OC2), // Type-A Rear
[4] = USB2_PORT_MID(OC3), // Type-A Rear
[5] = USB2_PORT_MID(OC_SKIP), // HDMI Audio
[6] = USB2_PORT_MID(OC_SKIP), // Bluetooth
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C
[1] = USB3_PORT_DEFAULT(OC_SKIP), // HDMI
[2] = USB3_PORT_DEFAULT(OC2), // Type-A Rear
[3] = USB3_PORT_DEFAULT(OC2), // Type-A Rear
[4] = USB3_PORT_DEFAULT(OC3), // Type-A Rear
}"
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi

38
src/mainboard/google/fizz/variants/karma/overridetree.cb
View File

@ -1,28 +1,32 @@
chip soc/intel/skylake
# Mapping of USB port # to device
#+----------------+-------+-----------------------------------+
#| Device | Port# | Rev |
#+----------------+-------+-----------------------------------+
#| USB A Side | 3 | 2/3 |
#| SD Card | 4 | |
#| Camera | 8 | |
#| Touchsreen | 10 | |
#+----------------+-------+-----------------------------------+
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Side
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Touchscreen
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Side
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader
register "power_limits_config" = "{
.psys_pmax = 151,
}"
device domain 0 on
device ref south_xhci on
# Mapping of USB port # to device
#+----------------+-------+-----------------------------------+
#| Device | Port# | Rev |
#+----------------+-------+-----------------------------------+
#| USB A Side | 3 | 2/3 |
#| SD Card | 4 | |
#| Camera | 8 | |
#| Touchsreen | 10 | |
#+----------------+-------+-----------------------------------+
register "usb2_ports" = "{
[2] = USB2_PORT_MID(OC2), // Type-A Side
[3] = USB2_PORT_MID(OC_SKIP), // Card reader
[7] = USB2_PORT_MID(OC_SKIP), // Camera
[9] = USB2_PORT_MID(OC_SKIP), // Touchscreen
}"
register "usb3_ports" = "{
[2] = USB3_PORT_DEFAULT(OC2), // Type-A Side
[3] = USB3_PORT_DEFAULT(OC_SKIP), // Card reader
}"
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi

31
src/mainboard/google/glados/variants/asuka/overridetree.cb
View File

@ -1,19 +1,24 @@
chip soc/intel/skylake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Card Reader
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (board)
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # PIC MCU
register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board)
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC0), // Type-C Port 1
[1] = USB2_PORT_MID(OC2), // Card Reader
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[4] = USB2_PORT_MID(OC2), // Type-A Port (board)
[6] = USB2_PORT_FLEX(OC_SKIP), // Camera
[7] = USB2_PORT_MID(OC_SKIP), // PIC MCU
[8] = USB2_PORT_LONG(OC3), // Type-A Port (board)
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC_SKIP), // Card Reader
[2] = USB3_PORT_DEFAULT(OC2), // Type-A Port (board)
[3] = USB3_PORT_DEFAULT(OC3), // Type-A Port (board)
}"
end
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""

21
src/mainboard/google/glados/variants/caroline/overridetree.cb
View File

@ -9,14 +9,6 @@ chip soc/intel/skylake
register "SlowSlewRateForGt" = "3" # Fast/16
register "SlowSlewRateForSa" = "0" # Fast/2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port (main)
register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub)
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub)
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, // touchpad
[PchSerialIoIndexI2C1] = PchSerialIoPci, // touchscreen
@ -38,6 +30,19 @@ chip soc/intel/skylake
register "tcc_offset" = "10"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), // Type-C Port (main)
[1] = USB2_PORT_MAX(OC_SKIP), // Type-C Port (sub)
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[6] = USB2_PORT_FLEX(OC_SKIP), // Camera
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port (main)
[1] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port (sub)
}"
end
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""ATML0001""

21
src/mainboard/google/glados/variants/cave/overridetree.cb
View File

@ -3,14 +3,6 @@ chip soc/intel/skylake
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port (board)
register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (flex)
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (board)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (flex)
# PL2 override 15W
register "power_limits_config" = "{
.tdp_pl2_override = 15,
@ -26,6 +18,19 @@ chip soc/intel/skylake
register "sdcard_cd_gpio" = "GPP_A7"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC_SKIP), // Type-C Port (board)
[1] = USB2_PORT_MAX(OC_SKIP), // Type-C Port (flex)
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[6] = USB2_PORT_FLEX(OC_SKIP), // Camera
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port (board)
[1] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port (flex)
}"
end
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""

29
src/mainboard/google/glados/variants/chell/overridetree.cb
View File

@ -3,18 +3,6 @@ chip soc/intel/skylake
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-C Port 2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # SD
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD
# PL2 override 15W
register "power_limits_config" = "{
.tdp_pl2_override = 15,
@ -27,6 +15,23 @@ chip soc/intel/skylake
register "tcc_offset" = "10"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC2), // Type-C Port 1
[1] = USB2_PORT_LONG(OC3), // Type-C Port 2
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[4] = USB2_PORT_MID(OC0), // Type-A Port
[6] = USB2_PORT_FLEX(OC_SKIP), // Camera
[8] = USB2_PORT_MID(OC_SKIP), // SD
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC2), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC3), // Type-C Port 2
[2] = USB3_PORT_DEFAULT(OC0), // Type-A Port
[3] = USB3_PORT_DEFAULT(OC_SKIP), // SD
}"
end
device ref i2c1 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""

29
src/mainboard/google/glados/variants/glados/overridetree.cb
View File

@ -3,18 +3,6 @@ chip soc/intel/skylake
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port (board)
register "usb2_ports[1]" = "USB2_PORT_MAX(OC3)" # Type-C Port (flex)
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port 1
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_MID(OC1)" # Type-A Port 2
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port (board)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port (flex)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2
# PL2 override 15W
register "power_limits_config" = "{
.tdp_pl2_override = 15,
@ -27,6 +15,23 @@ chip soc/intel/skylake
register "tcc_offset" = "10"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC2), // Type-C Port (board)
[1] = USB2_PORT_MAX(OC3), // Type-C Port (flex)
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[4] = USB2_PORT_MID(OC0), // Type-A Port 1
[6] = USB2_PORT_FLEX(OC_SKIP), // Camera
[8] = USB2_PORT_MID(OC1), // Type-A Port 2
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC2), // Type-C Port (board)
[1] = USB3_PORT_DEFAULT(OC3), // Type-C Port (flex)
[2] = USB3_PORT_DEFAULT(OC0), // Type-A Port 1
[3] = USB3_PORT_DEFAULT(OC1), // Type-A Port 2
}"
end
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""

29
src/mainboard/google/glados/variants/lars/overridetree.cb
View File

@ -1,18 +1,23 @@
chip soc/intel/skylake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card)
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # SD
register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board)
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC0), // Type-C Port 1
[1] = USB2_PORT_FLEX(OC_SKIP), // Camera
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[4] = USB2_PORT_MID(OC2), // Type-A Port (card)
[5] = USB2_PORT_MID(OC_SKIP), // SD
[8] = USB2_PORT_LONG(OC3), // Type-A Port (board)
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC_SKIP), // SD
[2] = USB3_PORT_DEFAULT(OC2), // Type-A Port (card)
[3] = USB3_PORT_DEFAULT(OC3), // Type-A Port (board)
}"
end
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""

29
src/mainboard/google/glados/variants/sentry/overridetree.cb
View File

@ -1,17 +1,5 @@
chip soc/intel/skylake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card)
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board)
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
# I2C0 is 3.3V
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
@ -19,6 +7,23 @@ chip soc/intel/skylake
register "sdcard_cd_gpio" = "GPP_A7"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC0), // Type-C Port 1
[1] = USB2_PORT_TYPE_C(OC1), // Type-C Port 2
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[4] = USB2_PORT_MID(OC2), // Type-A Port (card)
[6] = USB2_PORT_FLEX(OC_SKIP), // Camera
[8] = USB2_PORT_LONG(OC3), // Type-A Port (board)
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
[2] = USB3_PORT_DEFAULT(OC2), // Type-A Port (card)
[3] = USB3_PORT_DEFAULT(OC3), // Type-A Port (board)
}"
end
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""RAYD0001""

20
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -140,15 +140,6 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
# USB 2.0
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
# USB 3.0
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@ -231,6 +222,17 @@ chip soc/intel/skylake
device ref imgu on end
device ref ish off end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC0), // Type-C Port 1
[2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth
[4] = USB2_PORT_LONG(OC1), // Type-C Port 2
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
}"
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"

28
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -130,17 +130,6 @@ chip soc/intel/skylake
# RP 1 uses CLK SRC 1
register "PcieRpClkSrcNumber[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@ -251,7 +240,22 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref imgu on end
device ref south_xhci on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC0), // Type-C Port 1
[1] = USB2_PORT_MID(OC_SKIP), // Type-A Port
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[4] = USB2_PORT_LONG(OC1), // Type-C Port 2
[6] = USB2_PORT_MID(OC_SKIP), // Type-A Port
[8] = USB2_PORT_MID(OC_SKIP), // Type-A Port
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
[2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-A Port
}"
end
device ref south_xdci on end
device ref thermal on end
device ref cio on end

32
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -167,19 +167,6 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WiFi
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Rear camera
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Front camera
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
@ -276,7 +263,24 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref imgu off end
device ref south_xhci on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC0), // Type-C Port 0
[1] = USB2_PORT_LONG(OC1), // Type-C Port 1
[2] = USB2_PORT_MID(OC2), // Type-A Port
[3] = USB2_PORT_MID(OC_SKIP), // Card reader
[4] = USB2_PORT_MID(OC_SKIP), // WiFi
[5] = USB2_PORT_MID(OC_SKIP), // Rear camera
[6] = USB2_PORT_MID(OC_SKIP), // Front camera
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 0
[1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 1
[2] = USB3_PORT_DEFAULT(OC2), // Type-A Port
[3] = USB3_PORT_DEFAULT(OC_SKIP), // Card reader
}"
end
device ref south_xdci on end
device ref thermal on end
device ref cio off end

30
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -148,18 +148,6 @@ chip soc/intel/skylake
# RP 1, Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_SHORT(OC2)" # Type-A Port
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC0)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1
register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LTE module
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@ -282,7 +270,23 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref imgu on end
device ref south_xhci on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC1), // Type-C Port 1
[1] = USB2_PORT_SHORT(OC2), // Type-A Port
[2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth
[4] = USB2_PORT_LONG(OC0), // Type-C Port 2
[6] = USB2_PORT_SHORT(OC_SKIP), // H1
[8] = USB2_PORT_SHORT(OC_SKIP), // Camera
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC1), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC0), // Type-C Port 2
[2] = USB3_PORT_DEFAULT(OC2), // Type-A Port
[3] = USB3_PORT_DEFAULT(OC_SKIP), // LTE module
}"
end
device ref south_xdci on end
device ref thermal on end
device ref cio on end

22
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -147,16 +147,6 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
# USB 2.0
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # pogo port
# USB 3.0
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@ -247,6 +237,18 @@ chip soc/intel/skylake
device ref sa_thermal on end
device ref imgu on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC0), // Type-C Port 1
[2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth
[4] = USB2_PORT_LONG(OC1), // Type-C Port 2
[6] = USB2_PORT_LONG(OC_SKIP), // pogo port
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
}"
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"

25
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -137,17 +137,6 @@ chip soc/intel/skylake
# RP 1, Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_SHORT(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-A Port
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1
register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@ -233,6 +222,20 @@ chip soc/intel/skylake
device ref sa_thermal on end
device ref imgu off end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_SHORT(OC0), // Type-C Port 1
[1] = USB2_PORT_LONG(OC3), // Type-A Port
[2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth
[4] = USB2_PORT_LONG(OC1), // Type-C Port 2
[6] = USB2_PORT_SHORT(OC_SKIP), // H1
[8] = USB2_PORT_SHORT(OC_SKIP), // Camera
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
[2] = USB3_PORT_DEFAULT(OC3), // Type-A Port
}"
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"

28
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -139,17 +139,6 @@ chip soc/intel/skylake
# RP 1 uses CLK SRC 1
register "PcieRpClkSrcNumber[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@ -261,7 +250,22 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref imgu on end
device ref south_xhci on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC0), // Type-C Port 1
[1] = USB2_PORT_MID(OC_SKIP), // Type-A Port
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[4] = USB2_PORT_MAX(OC1), // Type-C Port 2
[6] = USB2_PORT_MID(OC_SKIP), // Type-A Port
[8] = USB2_PORT_MID(OC_SKIP), // Type-A Port
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
[1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
[2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-A Port
}"
end
device ref south_xdci on end
device ref thermal on end
device ref cio on end

60
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
View File

@ -46,35 +46,6 @@ chip soc/intel/skylake
# USB related
register "SsicPortEnable" = "1"
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* OTG */
[1] = USB2_PORT_MID(OC3), /* Touch Pad */
[2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */
[3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */
[4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */
[5] = USB2_PORT_MID(OC0), /* Front Panel */
[6] = USB2_PORT_MID(OC0), /* Front Panel */
[7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */
[12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
[13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC5), /* OTG */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */
[2] = USB3_PORT_DEFAULT(OC3), /* Flex */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */
[4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
[5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
}"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{
@ -107,6 +78,37 @@ chip soc/intel/skylake
}"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* OTG */
[1] = USB2_PORT_MID(OC3), /* Touch Pad */
[2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */
[3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */
[4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */
[5] = USB2_PORT_MID(OC0), /* Front Panel */
[6] = USB2_PORT_MID(OC0), /* Front Panel */
[7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */
[12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
[13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC5), /* OTG */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */
[2] = USB3_PORT_DEFAULT(OC3), /* Flex */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */
[4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
[5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
}"
end
device ref sa_thermal off end
device ref i2c2 off end
device ref i2c3 off end

42
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
View File

@ -74,26 +74,6 @@ chip soc/intel/skylake
# RP10, uses CLK SRC 4
register "PcieRpClkSrcNumber[9]" = "4"
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */
[1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */
[4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */
[5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */
[10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */
}"
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
@ -113,6 +93,28 @@ chip soc/intel/skylake
}"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */
[1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */
[4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */
[5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */
[10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */
}"
end
device ref imgu on end
device ref cio on end
device ref pcie_rp1 on end # x4 SLOT1

46
src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
View File

@ -113,28 +113,6 @@ chip soc/intel/skylake
# RP 9 uses CLK SRC 1#
register "PcieRpClkSrcNumber[8]" = "1"
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */
[1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */
[4] = USB2_PORT_MAX(OC1), /* Type-A Port */
[5] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[6] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[7] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[9] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */
[4] = USB3_PORT_DEFAULT(OC2), /* TYPE-A Port */
[5] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@ -154,6 +132,30 @@ chip soc/intel/skylake
register "sdcard_cd_gpio" = "GPP_G5"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */
[1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */
[4] = USB2_PORT_MAX(OC1), /* Type-A Port */
[5] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[6] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[7] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[9] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */
[4] = USB3_PORT_DEFAULT(OC2), /* TYPE-A Port */
[5] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
}"
end
device ref i2c2 off end
device ref i2c3 off end
device ref sata on end

60
src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
View File

@ -95,35 +95,6 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[8]" = "6"
register "PcieRpClkReqNumber[16]" = "7"
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC2), /* Type-C Port */
[1] = USB2_PORT_MAX(OC5), /* Front panel */
[2] = USB2_PORT_MAX(OC4), /* Back panel */
[3] = USB2_PORT_MAX(OC4), /* Back panel */
[4] = USB2_PORT_MAX(OC1), /* Back panel-1 */
[5] = USB2_PORT_MAX(OC1), /* Back panel */
[6] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
[7] = USB2_PORT_MAX(OC_SKIP), /* Front panel */
[8] = USB2_PORT_MAX(OC_SKIP), /* M.2 BT */
[9] = USB2_PORT_MAX(OC2), /* Front panel */
[10] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
[11] = USB2_PORT_MAX(OC_SKIP), /* Back panel-1 */
[12] = USB2_PORT_MAX(OC3), /* Back panel */
[13] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C Port */
[1] = USB3_PORT_DEFAULT(OC1), /* Back panel */
[2] = USB3_PORT_DEFAULT(OC1), /* Back panel */
[3] = USB3_PORT_DEFAULT(OC0), /* Back panel-2 */
[4] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[5] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel */
[6] = USB3_PORT_DEFAULT(OC2), /* Front Panel */
[7] = USB3_PORT_DEFAULT(OC2), /* Front Panel */
[8] = USB3_PORT_DEFAULT(OC3), /* Back panel */
[9] = USB3_PORT_DEFAULT(OC_SKIP), /* LAN */
}"
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
@ -160,6 +131,37 @@ chip soc/intel/skylake
}"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC2), /* Type-C Port */
[1] = USB2_PORT_MAX(OC5), /* Front panel */
[2] = USB2_PORT_MAX(OC4), /* Back panel */
[3] = USB2_PORT_MAX(OC4), /* Back panel */
[4] = USB2_PORT_MAX(OC1), /* Back panel-1 */
[5] = USB2_PORT_MAX(OC1), /* Back panel */
[6] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
[7] = USB2_PORT_MAX(OC_SKIP), /* Front panel */
[8] = USB2_PORT_MAX(OC_SKIP), /* M.2 BT */
[9] = USB2_PORT_MAX(OC2), /* Front panel */
[10] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
[11] = USB2_PORT_MAX(OC_SKIP), /* Back panel-1 */
[12] = USB2_PORT_MAX(OC3), /* Back panel */
[13] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C Port */
[1] = USB3_PORT_DEFAULT(OC1), /* Back panel */
[2] = USB3_PORT_DEFAULT(OC1), /* Back panel */
[3] = USB3_PORT_DEFAULT(OC0), /* Back panel-2 */
[4] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[5] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel */
[6] = USB3_PORT_DEFAULT(OC2), /* Front Panel */
[7] = USB3_PORT_DEFAULT(OC2), /* Front Panel */
[8] = USB3_PORT_DEFAULT(OC3), /* Back panel */
[9] = USB3_PORT_DEFAULT(OC_SKIP), /* LAN */
}"
end
device ref i2c2 off end
device ref i2c3 off end
device ref sata on end

33
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -117,21 +117,6 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC0), /* Type-C Port 1 */
[1] = USB2_PORT_TYPE_C(OC1), /* Type-C Port 2 */
[2] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
[4] = USB2_PORT_MID(OC2), /* Type-A Port (card) */
[6] = USB2_PORT_FLEX(OC_SKIP), /* Camera */
[8] = USB2_PORT_LONG(OC3), /* Type-A Port (board) */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), /* Type-C Port 1 */
[1] = USB3_PORT_DEFAULT(OC1), /* Type-C Port 2 */
[2] = USB3_PORT_DEFAULT(OC2), /* Type-A Port (card) */
[3] = USB3_PORT_DEFAULT(OC3), /* Type-A Port (board) */
}"
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
@ -164,7 +149,23 @@ chip soc/intel/skylake
device domain 0 on
device ref igpu on end
device ref sa_thermal on end
device ref south_xhci on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC0), /* Type-C Port 1 */
[1] = USB2_PORT_TYPE_C(OC1), /* Type-C Port 2 */
[2] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
[4] = USB2_PORT_MID(OC2), /* Type-A Port (card) */
[6] = USB2_PORT_FLEX(OC_SKIP), /* Camera */
[8] = USB2_PORT_LONG(OC3), /* Type-A Port (board) */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), /* Type-C Port 1 */
[1] = USB3_PORT_DEFAULT(OC1), /* Type-C Port 2 */
[2] = USB3_PORT_DEFAULT(OC2), /* Type-A Port (card) */
[3] = USB3_PORT_DEFAULT(OC3), /* Type-A Port (board) */
}"
end
device ref thermal on end
device ref i2c0 on
chip drivers/i2c/generic

61
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@ -125,35 +125,6 @@ chip soc/intel/skylake
# USB related
register "SsicPortEnable" = "1"
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* OTG */
[1] = USB2_PORT_MID(OC3), /* Touch Pad */
[2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */
[3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */
[4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */
[5] = USB2_PORT_MID(OC0), /* Front Panel */
[6] = USB2_PORT_MID(OC0), /* Front Panel */
[7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */
[12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
[13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC5), /* OTG */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */
[2] = USB3_PORT_DEFAULT(OC3), /* Flex */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */
[4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
[5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
}"
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
@ -197,7 +168,37 @@ chip soc/intel/skylake
device domain 0 on
device ref igpu on end
device ref south_xhci on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* OTG */
[1] = USB2_PORT_MID(OC3), /* Touch Pad */
[2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */
[3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */
[4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */
[5] = USB2_PORT_MID(OC0), /* Front Panel */
[6] = USB2_PORT_MID(OC0), /* Front Panel */
[7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */
[12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
[13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC5), /* OTG */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */
[2] = USB3_PORT_DEFAULT(OC3), /* Flex */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */
[4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
[5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
}"
end
device ref thermal on end
device ref i2c0 on end
device ref i2c1 on end

25
src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb
View File

@ -8,19 +8,24 @@ chip soc/intel/skylake
register "PcieRpEnable[ 3]" = "1"
register "PcieRpEnable[11]" = "1"
register "usb2_ports[5]" = "USB2_PORT_LONG(OC2)"
register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)"
register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)"
register "usb2_ports[8]" = "USB2_PORT_MID(OC4)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
register "SataPortsEnable[3]" = "1"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[5] = USB2_PORT_LONG(OC2),
[6] = USB2_PORT_LONG(OC3),
[7] = USB2_PORT_LONG(OC3),
[8] = USB2_PORT_MID(OC4),
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0),
[1] = USB3_PORT_DEFAULT(OC0),
[2] = USB3_PORT_DEFAULT(OC1),
[3] = USB3_PORT_DEFAULT(OC1),
}"
end
device ref pcie_rp1 on end
device ref pcie_rp2 on end
device ref pcie_rp3 on end

38
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -125,24 +125,6 @@ chip soc/intel/skylake
register "PcieRpClkSrcNumber[10]" = "3"
register "PcieRpClkSrcNumber[11]" = "3"
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
[1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
[2] = USB2_PORT_MID(OC_SKIP), /* WiFi */
[3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
[4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
[5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
[6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
[7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
}"
# PL2 override 25W
register "power_limits_config" = "{
.tdp_pl2_override = 25,
@ -154,7 +136,25 @@ chip soc/intel/skylake
device domain 0 on
device ref igpu on end
device ref sa_thermal on end
device ref south_xhci on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
[1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */
[2] = USB2_PORT_MID(OC_SKIP), /* WiFi */
[3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
[4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */
[5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
[6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */
[7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */
}"
end
device ref south_xdci on end
device ref thermal on end
device ref heci1 on end

37
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@ -152,23 +152,6 @@ chip soc/intel/skylake
# RP 9 shares CLKSRC5# with RP 6
register "PcieRpClkSrcNumber[8]" = "5"
# USB 2.0 enable ports 1-8, disable ports 9-12
register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port
register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot
# USB 3.0 enable ports 1-4, disable ports 5-6
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
@ -185,7 +168,25 @@ chip soc/intel/skylake
device domain 0 on
device ref igpu on end
device ref south_xhci on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
[1] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
[2] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
[3] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
[4] = USB2_PORT_SHORT(OC_SKIP), // Type-A Port
[5] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
[6] = USB2_PORT_SHORT(OC_SKIP), // TYPE-A Port
[7] = USB2_PORT_SHORT(OC_SKIP), // mPCIe slot
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
[1] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
[2] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
[3] = USB3_PORT_DEFAULT(OC_SKIP), // TYPE-A Port
}"
end
device ref heci1 on end
device ref sata on end
device ref pcie_rp1 on end

32
src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb
View File

@ -1,17 +1,23 @@
chip soc/intel/skylake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right)
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC_SKIP), // Type-C Port
[1] = USB2_PORT_MID(OC0), // Type-A Port (right)
[2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[3] = USB2_PORT_FLEX(OC_SKIP), // Camera
[5] = USB2_PORT_FLEX(OC2), // Type-A Port (left)
[6] = USB2_PORT_MID(OC_SKIP), // SD
}"
# OC1 should be for Type-C but it seems to not have been wired, according to
# the available schematics, even though it is labeled as USB_OC_TYPEC.
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
device domain 0 on end
# OC1 should be for Type-C but it seems to not have been wired, according to
# the available schematics, even though it is labeled as USB_OC_TYPEC.
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port
[1] = USB3_PORT_DEFAULT(OC0), // Type-A Port (right)
[2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port
}"
end
end
end

37
src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb
View File

@ -5,23 +5,28 @@ chip soc/intel/skylake
# SRCCLKREQ2# for NVMe per schematic
register "PcieRpClkReqNumber[8]" = "2"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
# OC0 should be for Type-C but it seems to not have been wired, according to
# the available schematics, even though it is labeled as USB_OC_TYPEC.
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC_SKIP), // Type-C Port
[1] = USB2_PORT_MID(OC1), // Type-A Port (right)
[2] = USB2_PORT_MID(OC1), // Type-A Port (right)
[3] = USB2_PORT_FLEX(OC2), // Type-A Port (left)
[4] = USB2_PORT_FLEX(OC2), // Type-A Port (left)
[5] = USB2_PORT_MID(OC_SKIP), // Bluetooth
[6] = USB2_PORT_FLEX(OC_SKIP), // Camera
[7] = USB2_PORT_FLEX(OC_SKIP), // SD
}"
# OC0 should be for Type-C but it seems to not have been wired, according to
# the available schematics, even though it is labeled as USB_OC_TYPEC.
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port
[1] = USB3_PORT_DEFAULT(OC1), // Type-A Port (right)
[2] = USB3_PORT_DEFAULT(OC1), // Type-A Port (right)
[3] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port
}"
end
device ref pcie_rp5 on end
end
end

51
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
View File

@ -15,32 +15,33 @@ chip soc/intel/skylake
# This board has an IGD with no output.
register "PrimaryDisplay" = "Display_Auto"
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC0), /* USB 2 */
[1] = USB2_PORT_MID(OC0), /* USB 3 */
[2] = USB2_PORT_MID(OC1), /* USB 4 */
[3] = USB2_PORT_MID(OC1), /* USB 5 */
[4] = USB2_PORT_MID(OC2), /* USB 0 */
[5] = USB2_PORT_MID(OC2), /* USB 1 */
[8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
[9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */
[10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
[11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
[12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */
[13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */
[14] = USB2_PORT_MID(OC0), /* Unknown */
[15] = USB2_PORT_MID(OC0), /* Unknown */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */
[1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
[2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
[3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
[4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */
}"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC0), /* USB 2 */
[1] = USB2_PORT_MID(OC0), /* USB 3 */
[2] = USB2_PORT_MID(OC1), /* USB 4 */
[3] = USB2_PORT_MID(OC1), /* USB 5 */
[4] = USB2_PORT_MID(OC2), /* USB 0 */
[5] = USB2_PORT_MID(OC2), /* USB 1 */
[8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
[9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */
[10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
[11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
[12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */
[13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */
[14] = USB2_PORT_MID(OC0), /* Unknown */
[15] = USB2_PORT_MID(OC0), /* Unknown */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */
[1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
[2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
[3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
[4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */
}"
end
device ref peg0 on
# Slot JPCIE3
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"

51
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
View File

@ -14,32 +14,33 @@ chip soc/intel/skylake
# FIXME: find out why FSP crashes without this
register "PchHdaVcType" = "Vc1"
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC0), /* USB 2 */
[1] = USB2_PORT_MID(OC0), /* USB 3 */
[2] = USB2_PORT_MID(OC1), /* USB 4 */
[3] = USB2_PORT_MID(OC1), /* USB 5 */
[4] = USB2_PORT_MID(OC2), /* USB 0 */
[5] = USB2_PORT_MID(OC2), /* USB 1 */
[8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
[9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */
[10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
[11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
[12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */
[13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */
[14] = USB2_PORT_MID(OC0), /* Unknown */
[15] = USB2_PORT_MID(OC0), /* Unknown */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */
[1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
[2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
[3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
[4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */
}"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC0), /* USB 2 */
[1] = USB2_PORT_MID(OC0), /* USB 3 */
[2] = USB2_PORT_MID(OC1), /* USB 4 */
[3] = USB2_PORT_MID(OC1), /* USB 5 */
[4] = USB2_PORT_MID(OC2), /* USB 0 */
[5] = USB2_PORT_MID(OC2), /* USB 1 */
[8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
[9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */
[10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
[11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
[12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */
[13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */
[14] = USB2_PORT_MID(OC0), /* Unknown */
[15] = USB2_PORT_MID(OC0), /* Unknown */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */
[1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
[2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
[3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
[4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */
}"
end
device ref peg0 on end # unused
device ref peg1 on
# Slot JPCIE1

47
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
View File

@ -11,31 +11,32 @@ chip soc/intel/skylake
register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
[1] = USB2_PORT_MID(OC3), /* USB 8 (3.0) */
[2] = USB2_PORT_MID(OC1), /* USB 3 */
[3] = USB2_PORT_MID(OC1), /* USB 2 */
[4] = USB2_PORT_MID(OC2), /* USB 1 */
[5] = USB2_PORT_MID(OC2), /* USB 0 */
[6] = USB2_PORT_MID(OC0), /* USB 5 */
[7] = USB2_PORT_MID(OC0), /* USB 4 */
[8] = USB2_PORT_MID(OC_SKIP), /* IPMI USB HUB */
[9] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */
[10] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
[11] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
[1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
[2] = USB3_PORT_DEFAULT(OC5), /* USB 10 */
[3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
[4] = USB3_PORT_DEFAULT(OC3), /* USB 8 */
}"
device domain 0 on
subsystemid 0x15d9 0x0896 inherit
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */
[1] = USB2_PORT_MID(OC3), /* USB 8 (3.0) */
[2] = USB2_PORT_MID(OC1), /* USB 3 */
[3] = USB2_PORT_MID(OC1), /* USB 2 */
[4] = USB2_PORT_MID(OC2), /* USB 1 */
[5] = USB2_PORT_MID(OC2), /* USB 0 */
[6] = USB2_PORT_MID(OC0), /* USB 5 */
[7] = USB2_PORT_MID(OC0), /* USB 4 */
[8] = USB2_PORT_MID(OC_SKIP), /* IPMI USB HUB */
[9] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */
[10] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */
[11] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC4), /* USB 7 */
[1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */
[2] = USB3_PORT_DEFAULT(OC5), /* USB 10 */
[3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */
[4] = USB3_PORT_DEFAULT(OC3), /* USB 8 */
}"
end
device ref peg0 on
# Slot JPCIE6
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"

53
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb
View File

@ -15,33 +15,34 @@ chip soc/intel/skylake
# This board has an IGD with no output.
register "PrimaryDisplay" = "Display_Auto"
# NB: Overcurrent OCx values untested
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC3), /* USB 6 (3.0) */
[1] = USB2_PORT_MID(OC3), /* USB 7 (3.0) */
[2] = USB2_PORT_MID(OC2), /* USB 0 */
[3] = USB2_PORT_MID(OC2), /* USB 1 */
[4] = USB2_PORT_MID(OC1), /* USB 4 */
[5] = USB2_PORT_MID(OC1), /* USB 5 */
[8] = USB2_PORT_MID(OC0), /* USB 2 */
[9] = USB2_PORT_MID(OC0), /* USB 3 */
[10] = USB2_PORT_MID(OC5), /* USB 9 (3.0) */
[11] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */
[12] = USB2_PORT_MID(OC4), /* USB 8 (3.0) */
[13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */
[14] = USB2_PORT_MID(OC0), /* Unknown */
[15] = USB2_PORT_MID(OC0), /* Unknown */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC3), /* USB 6 */
[1] = USB3_PORT_DEFAULT(OC3), /* USB 7 */
[2] = USB3_PORT_DEFAULT(OC4), /* USB 8 */
[3] = USB3_PORT_DEFAULT(OC5), /* USB 9 */
[4] = USB3_PORT_DEFAULT(OC5), /* USB 10 */
}"
device domain 0 on
device ref south_xhci on
# NB: Overcurrent OCx values untested
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC3), /* USB 6 (3.0) */
[1] = USB2_PORT_MID(OC3), /* USB 7 (3.0) */
[2] = USB2_PORT_MID(OC2), /* USB 0 */
[3] = USB2_PORT_MID(OC2), /* USB 1 */
[4] = USB2_PORT_MID(OC1), /* USB 4 */
[5] = USB2_PORT_MID(OC1), /* USB 5 */
[8] = USB2_PORT_MID(OC0), /* USB 2 */
[9] = USB2_PORT_MID(OC0), /* USB 3 */
[10] = USB2_PORT_MID(OC5), /* USB 9 (3.0) */
[11] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */
[12] = USB2_PORT_MID(OC4), /* USB 8 (3.0) */
[13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */
[14] = USB2_PORT_MID(OC0), /* Unknown */
[15] = USB2_PORT_MID(OC0), /* Unknown */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC3), /* USB 6 */
[1] = USB3_PORT_DEFAULT(OC3), /* USB 7 */
[2] = USB3_PORT_DEFAULT(OC4), /* USB 8 */
[3] = USB3_PORT_DEFAULT(OC5), /* USB 9 */
[4] = USB3_PORT_DEFAULT(OC5), /* USB 10 */
}"
end
device ref peg0 on
# Slot JSXB1B
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X"