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soc/intel/common: Extend WAIT_FOR_DP_MODE_ENTRY_TIMEOUT_MS to 1500ms

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Some dongles require more time to be ready,
this CL extedns the DP mode entry timeout from 0.5s to 1.5s and make
sure the tested dongle display works.

Before:
[WARN ]  DP not ready after 500ms. Abort.

After:
[INFO ]  DP ready after 1211 ms

BUG=b:348309582
TEST=emerge coreboot
     verify tested dongles and monitors display works

Change-Id: I22d7800b50f6f7de9f147ae6998a5015d0dc0be9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83206
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Tony Huang
2024-06-25 15:57:44 +08:00
committed by Stefan Reinauer
parent 516d05f43d
commit c7c8cf2edd
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/common/block/tcss/tcss.c
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@@ -21,7 +21,7 @@
#define BIAS_CTRL_VW_INDEX_SHIFT 16
#define BIAS_CTRL_BIT_POS_SHIFT 8
#define WAIT_FOR_DISPLAYPORT_TIMEOUT_MS 1000
#define WAIT_FOR_DP_MODE_ENTRY_TIMEOUT_MS 500
#define WAIT_FOR_DP_MODE_ENTRY_TIMEOUT_MS 1500
#define WAIT_FOR_HPD_TIMEOUT_MS 3000
static uint32_t tcss_make_conn_cmd(int u, int u3, int u2, int ufp, int hsl,