cpu/intel/common: Move intel_ht_sibling() to common folder

Make intel_ht_sibling() available on all platforms.

Will be used in MP init to only write "Core" MSRs from one thread
on HyperThreading enabled platforms, to prevent race conditions and
resulting #GP if MSRs are written twice or are already locked.

Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/common/Kconfig

@@ -22,4 +22,7 @@ config SET_IA32_FC_LOCK_BIT
 config CPU_INTEL_COMMON_TIMEBASE
 	bool
 
+config CPU_INTEL_COMMON_HYPERTHREADING
+	bool
+
 endif

src/cpu/intel/common/Makefile.inc

@@ -1,4 +1,5 @@
-ramstage-y += common_init.c
+ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
+ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c
 
 ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y)
 bootblock-y += fsb.c

src/cpu/intel/common/common.h

@@ -15,6 +15,8 @@
 #ifndef _CPU_INTEL_COMMON_H
 #define _CPU_INTEL_COMMON_H
 
+#include <stdint.h>
+
 void set_vmx_and_lock(void);
 void set_feature_ctrl_vmx(void);
 void set_feature_ctrl_lock(void);
@@ -27,4 +29,9 @@ void set_feature_ctrl_lock(void);
 struct cppc_config;
 void cpu_init_cppc_config(struct cppc_config *config, u32 version);
 
+/*
+ * Returns true if it's not thread 0 on a hyperthreading enabled core.
+ */
+bool intel_ht_sibling(void);
+
 #endif

src/cpu/intel/common/hyperthreading.c

@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/common/common.h>
+#include <arch/cpu.h>
+
+/*
+ * Return true if running thread does not have the smallest lapic ID
+ * within a CPU core.
+ */
+bool intel_ht_sibling(void)
+{
+	struct cpuid_result result;
+	unsigned int core_ids, apic_ids, threads;
+
+	/* Is Hyper-Threading supported */
+	if (!(cpuid_edx(1) & CPUID_FEAURE_HTT))
+		return false;
+
+	apic_ids = 1;
+	if (cpuid_eax(0) >= 1)
+		apic_ids = (cpuid_ebx(1) >> 16) & 0xff;
+	if (apic_ids == 0)
+		apic_ids = 1;
+
+	core_ids = 1;
+	if (cpuid_eax(0) >= 4) {
+		result = cpuid_ext(4, 0);
+		core_ids += (result.eax >> 26) & 0x3f;
+	}
+
+	threads = (apic_ids / core_ids);
+	return !!(lapicid() & (threads - 1));
+}