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bonw15: Fix SSD2 and DGPU PCIe definitions

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Change-Id: I717a0b87927e3084e56651f9241ee8ae086caf80
This commit is contained in:
Jeremy Soller
2023-06-22 09:28:18 -06:00
parent 2cb78b9a76
commit 6e1a07ca56
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/system76/rpl/variants/bonw15/overridetree.cb
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@@ -42,19 +42,19 @@ chip soc/intel/alderlake
end end
device ref pcie5_0 on device ref pcie5_0 on
# CPU PCIe RP#2 x8, Clock 14 (DGPU) # CPU PCIe RP#3 x4, CLKOUT 2, CLKREQ 11 (SSD2)
register "cpu_pcie_rp[CPU_RP(2)]" = "{ register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 14, .clk_src = 2,
.clk_req = 14, .clk_req = 11,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
}" }"
end end
device ref pcie5_1 on device ref pcie5_1 on
# CPU PCIe RP#3 x4, Clock 2 (SSD2) # CPU PCIe RP#2 x8, Clock 14 (DGPU)
register "cpu_pcie_rp[CPU_RP(3)]" = "{ register "cpu_pcie_rp[CPU_RP(3)]" = "{
.clk_src = 2, .clk_src = 14,
.clk_req = 2, .clk_req = 14,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
}" }"
end end