soc/intel/skylake: Move soc_acpi_name()
Done for consistency with newer platforms. Change-Id: I1250c4514e1512e748bfc65c3f9f9da4ff1ef78e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50939 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
@@ -548,112 +548,3 @@ int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint
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return GPE0_REG_MAX;
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return GPE0_REG_MAX;
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}
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}
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const char *soc_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type == DEVICE_PATH_USB) {
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switch (dev->path.usb.port_type) {
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case 0:
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/* Root Hub */
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return "RHUB";
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case 2:
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/* USB2 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "HS01";
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case 1: return "HS02";
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case 2: return "HS03";
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case 3: return "HS04";
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case 4: return "HS05";
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case 5: return "HS06";
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case 6: return "HS07";
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case 7: return "HS08";
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case 8: return "HS09";
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case 9: return "HS10";
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}
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break;
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case 3:
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/* USB3 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "SS01";
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case 1: return "SS02";
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case 2: return "SS03";
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case 3: return "SS04";
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case 4: return "SS05";
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case 5: return "SS06";
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}
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break;
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}
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return NULL;
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}
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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/* Match functions 0 and 1 for possible GPUs on a secondary bus */
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if (dev->bus && dev->bus->secondary > 0) {
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switch (PCI_FUNC(dev->path.pci.devfn)) {
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case 0: return "DEV0";
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case 1: return "DEV1";
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}
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return NULL;
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}
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switch (dev->path.pci.devfn) {
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case SA_DEVFN_ROOT: return "MCHC";
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case SA_DEVFN_PEG0: return "PEGP";
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case SA_DEVFN_IGD: return "GFX0";
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case PCH_DEVFN_ISH: return "ISHB";
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case PCH_DEVFN_XHCI: return "XHCI";
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case PCH_DEVFN_USBOTG: return "XDCI";
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case PCH_DEVFN_THERMAL: return "THRM";
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case PCH_DEVFN_CIO: return "ICIO";
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case PCH_DEVFN_I2C0: return "I2C0";
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case PCH_DEVFN_I2C1: return "I2C1";
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case PCH_DEVFN_I2C2: return "I2C2";
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case PCH_DEVFN_I2C3: return "I2C3";
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case PCH_DEVFN_CSE: return "CSE1";
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case PCH_DEVFN_CSE_2: return "CSE2";
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case PCH_DEVFN_CSE_IDER: return "CSED";
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case PCH_DEVFN_CSE_KT: return "CSKT";
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case PCH_DEVFN_CSE_3: return "CSE3";
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case PCH_DEVFN_SATA: return "SATA";
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case PCH_DEVFN_UART2: return "UAR2";
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case PCH_DEVFN_I2C4: return "I2C4";
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case PCH_DEVFN_I2C5: return "I2C5";
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case PCH_DEVFN_PCIE1: return "RP01";
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case PCH_DEVFN_PCIE2: return "RP02";
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case PCH_DEVFN_PCIE3: return "RP03";
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case PCH_DEVFN_PCIE4: return "RP04";
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case PCH_DEVFN_PCIE5: return "RP05";
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case PCH_DEVFN_PCIE6: return "RP06";
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case PCH_DEVFN_PCIE7: return "RP07";
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case PCH_DEVFN_PCIE8: return "RP08";
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case PCH_DEVFN_PCIE9: return "RP09";
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case PCH_DEVFN_PCIE10: return "RP10";
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case PCH_DEVFN_PCIE11: return "RP11";
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case PCH_DEVFN_PCIE12: return "RP12";
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case PCH_DEVFN_PCIE13: return "RP13";
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case PCH_DEVFN_PCIE14: return "RP14";
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case PCH_DEVFN_PCIE15: return "RP15";
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case PCH_DEVFN_PCIE16: return "RP16";
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case PCH_DEVFN_UART0: return "UAR0";
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case PCH_DEVFN_UART1: return "UAR1";
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case PCH_DEVFN_GSPI0: return "SPI0";
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case PCH_DEVFN_GSPI1: return "SPI1";
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case PCH_DEVFN_EMMC: return "EMMC";
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case PCH_DEVFN_SDIO: return "SDIO";
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case PCH_DEVFN_SDCARD: return "SDXC";
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case PCH_DEVFN_P2SB: return "P2SB";
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case PCH_DEVFN_PMC: return "PMC_";
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case PCH_DEVFN_HDA: return "HDAS";
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case PCH_DEVFN_SMBUS: return "SBUS";
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case PCH_DEVFN_SPI: return "FSPI";
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case PCH_DEVFN_GBE: return "IGBE";
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case PCH_DEVFN_TRACEHUB:return "THUB";
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}
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return NULL;
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}
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@@ -48,6 +48,117 @@ static const struct pcie_rp_group pch_h_rp_groups[] = {
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{ 0 }
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{ 0 }
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};
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};
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#if CONFIG(HAVE_ACPI_TABLES)
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const char *soc_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type == DEVICE_PATH_USB) {
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switch (dev->path.usb.port_type) {
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case 0:
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/* Root Hub */
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return "RHUB";
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case 2:
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/* USB2 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "HS01";
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case 1: return "HS02";
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case 2: return "HS03";
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case 3: return "HS04";
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case 4: return "HS05";
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case 5: return "HS06";
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case 6: return "HS07";
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case 7: return "HS08";
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case 8: return "HS09";
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case 9: return "HS10";
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}
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break;
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case 3:
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/* USB3 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "SS01";
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case 1: return "SS02";
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case 2: return "SS03";
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case 3: return "SS04";
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case 4: return "SS05";
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case 5: return "SS06";
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}
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break;
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}
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return NULL;
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}
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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/* Match functions 0 and 1 for possible GPUs on a secondary bus */
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if (dev->bus && dev->bus->secondary > 0) {
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switch (PCI_FUNC(dev->path.pci.devfn)) {
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case 0: return "DEV0";
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case 1: return "DEV1";
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}
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return NULL;
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}
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switch (dev->path.pci.devfn) {
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case SA_DEVFN_ROOT: return "MCHC";
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case SA_DEVFN_PEG0: return "PEGP";
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case SA_DEVFN_IGD: return "GFX0";
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case PCH_DEVFN_ISH: return "ISHB";
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case PCH_DEVFN_XHCI: return "XHCI";
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case PCH_DEVFN_USBOTG: return "XDCI";
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case PCH_DEVFN_THERMAL: return "THRM";
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case PCH_DEVFN_CIO: return "ICIO";
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case PCH_DEVFN_I2C0: return "I2C0";
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case PCH_DEVFN_I2C1: return "I2C1";
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case PCH_DEVFN_I2C2: return "I2C2";
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case PCH_DEVFN_I2C3: return "I2C3";
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case PCH_DEVFN_CSE: return "CSE1";
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case PCH_DEVFN_CSE_2: return "CSE2";
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case PCH_DEVFN_CSE_IDER: return "CSED";
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case PCH_DEVFN_CSE_KT: return "CSKT";
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case PCH_DEVFN_CSE_3: return "CSE3";
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case PCH_DEVFN_SATA: return "SATA";
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case PCH_DEVFN_UART2: return "UAR2";
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case PCH_DEVFN_I2C4: return "I2C4";
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case PCH_DEVFN_I2C5: return "I2C5";
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case PCH_DEVFN_PCIE1: return "RP01";
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case PCH_DEVFN_PCIE2: return "RP02";
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case PCH_DEVFN_PCIE3: return "RP03";
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case PCH_DEVFN_PCIE4: return "RP04";
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case PCH_DEVFN_PCIE5: return "RP05";
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case PCH_DEVFN_PCIE6: return "RP06";
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case PCH_DEVFN_PCIE7: return "RP07";
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case PCH_DEVFN_PCIE8: return "RP08";
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case PCH_DEVFN_PCIE9: return "RP09";
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case PCH_DEVFN_PCIE10: return "RP10";
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case PCH_DEVFN_PCIE11: return "RP11";
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case PCH_DEVFN_PCIE12: return "RP12";
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case PCH_DEVFN_PCIE13: return "RP13";
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case PCH_DEVFN_PCIE14: return "RP14";
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case PCH_DEVFN_PCIE15: return "RP15";
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case PCH_DEVFN_PCIE16: return "RP16";
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case PCH_DEVFN_UART0: return "UAR0";
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case PCH_DEVFN_UART1: return "UAR1";
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case PCH_DEVFN_GSPI0: return "SPI0";
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case PCH_DEVFN_GSPI1: return "SPI1";
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case PCH_DEVFN_EMMC: return "EMMC";
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case PCH_DEVFN_SDIO: return "SDIO";
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case PCH_DEVFN_SDCARD: return "SDXC";
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case PCH_DEVFN_P2SB: return "P2SB";
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case PCH_DEVFN_PMC: return "PMC_";
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case PCH_DEVFN_HDA: return "HDAS";
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case PCH_DEVFN_SMBUS: return "SBUS";
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case PCH_DEVFN_SPI: return "FSPI";
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case PCH_DEVFN_GBE: return "IGBE";
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case PCH_DEVFN_TRACEHUB:return "THUB";
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}
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return NULL;
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}
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#endif
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void soc_init_pre_device(void *chip_info)
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void soc_init_pre_device(void *chip_info)
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{
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{
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/* Snapshot the current GPIO IRQ polarities. FSP is setting a
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/* Snapshot the current GPIO IRQ polarities. FSP is setting a
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