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soc/intel: Factor out identical acpigen GPIO helpers

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Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-02-19 19:42:10 +01:00
parent 6bd99f9ada
commit 98f672a5ea
15 changed files with 50 additions and 222 deletions
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1
src/soc/intel/alderlake/Kconfig
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@@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU

37
src/soc/intel/alderlake/acpi.c
View File

@@ -301,40 +301,3 @@ int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;
}
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
}

1
src/soc/intel/cannonlake/Kconfig
View File

@@ -87,6 +87,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CNVI

37
src/soc/intel/cannonlake/acpi.c
View File

@@ -206,43 +206,6 @@ int soc_madt_sci_irq_polarity(int sci)
return MP_IRQ_POLARITY_HIGH;
}
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
}
static unsigned long soc_fill_dmar(unsigned long current)
{
struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);

3
src/soc/intel/common/block/acpi/Kconfig
View File

@@ -5,6 +5,9 @@ config SOC_INTEL_COMMON_BLOCK_ACPI
help
Intel Processor common code for ACPI
config SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
bool
config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
bool
depends on HAVE_ACPI_TABLES

1
src/soc/intel/common/block/acpi/Makefile.inc
View File

@@ -1,4 +1,5 @@
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO) += gpio.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT) += lpit.c
ramstage-$(CONFIG_ACPI_BERT) += acpi_bert.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c

40
src/soc/intel/common/block/acpi/gpio.c Normal file
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@@ -0,0 +1,40 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h>
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
}

1
src/soc/intel/elkhartlake/Kconfig
View File

@@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG

37
src/soc/intel/elkhartlake/acpi.c
View File

@@ -269,40 +269,3 @@ int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;
}
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
}

1
src/soc/intel/jasperlake/Kconfig
View File

@@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG

37
src/soc/intel/jasperlake/acpi.c
View File

@@ -296,40 +296,3 @@ int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;
}
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
}

1
src/soc/intel/skylake/Kconfig
View File

@@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG

37
src/soc/intel/skylake/acpi.c
View File

@@ -657,40 +657,3 @@ const char *soc_acpi_name(const struct device *dev)
return NULL;
}
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
}

1
src/soc/intel/tigerlake/Kconfig
View File

@@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG

37
src/soc/intel/tigerlake/acpi.c
View File

@@ -296,40 +296,3 @@ int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;
}
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
/* op (gpio_num) */
acpigen_emit_namestring(op);
acpigen_write_integer(gpio_num);
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
}
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
}