soc/intel/common/cse: Add support for stitching CSE components
This change adds support for allowing mainboards to stitch CSE components during build time instead of adding a pre-built CSE binary. Several Kconfig options are added to allow mainboard to provide the file names for different CSE region components. This makes use of the newly added cse_serger and cse_fpt tools to create following partitions: 1. BP1 - RO 2. BP2 - RW 3. Layout In addition to this, it accepts CSE data partition as an input using Kconfig CSE_DATA_FILE. All these partitions are then assembled together as per the following mainboard FMAP regions: 1. BP1(RO) : CSE_RO 2. BP2(RW) : CSE_RW 3. Layout : CSE_LAYOUT 4. Data : CSE_DATA Finally, it generates the target $(OBJ_ME_BIN) which is used to put together the binary in final coreboot.rom image. Several helper functions are added to soc/intel/Makefile.inc to allow SoCs to define which components use: 1. Decomposed files: Files decomposed from Intel release CSE binary in FPT format. 2. Input files: Mainboard provided input files using corresponding Kconfigs. 3. Dummy: Components that are required to have dummy entries in BPDT header. These helpers are added to soc/intel/Makefile.inc to ensure that the functions are defined by the time the invocations are encountered in SoC Makefile.inc. BUG=b:189177580 Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
44
src/soc/intel/Makefile.inc
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44
src/soc/intel/Makefile.inc
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@@ -0,0 +1,44 @@
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ifeq ($(CONFIG_STITCH_ME_BIN),y)
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objcse := $(obj)/cse
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additional-dirs += $(objcse)
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define cse_input_path
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$(call strip_quotes,$(CONFIG_CSE_COMPONENTS_PATH))/$(call strip_quotes,$(1))
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endef
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define cse_add_dummy
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$(eval cse_$(1)_ingredients+=$(2))
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endef
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define cse_add_dummy_to_bp1_bp2
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$(call cse_add_dummy,bp1,$(1))
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$(call cse_add_dummy,bp2,$(1))
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endef
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define cse_add_file
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$(eval cse_$(3)_ingredients+=$(4))
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$(eval file=$(2))
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$(eval $(4)-file=$(file))
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$(eval $(1)+=$(if $(filter $(file),$($(1))),,$(file)))
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endef
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define cse_add_decomp
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$(call cse_add_file,cse_decomp_files,$(objcse)/$(2),$(1),$(2))
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endef
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define cse_add_decomp_to_bp1_bp2
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$(call cse_add_decomp,bp1,$(1))
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$(call cse_add_decomp,bp2,$(1))
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endef
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define cse_add_input
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$(call cse_add_file,cse_input_files,$(call cse_input_path,$(CONFIG_CSE_$(2)_FILE)),$(1),$(2))
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endef
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define cse_add_input_to_bp1_bp2
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$(call cse_add_input,bp1,$(1))
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$(call cse_add_input,bp2,$(1))
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endef
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endif
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@@ -85,3 +85,67 @@ config SOC_INTEL_CSE_SET_EOP
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This config ensures coreboot will send the CSE the End-of-POST message
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just prior to loading the payload. This is a security feature so the
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CSE will no longer respond to Pre-Boot commands.
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if STITCH_ME_BIN
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config CSE_COMPONENTS_PATH
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string "Path to directory containing all CSE input components to stitch"
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default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/firmware"
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help
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This is the file path containing all the input CSE component files.
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These will be used by cse_serger tool to stitch CSE image.
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config CSE_FPT_FILE
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string "Name of CSE FPT file"
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default "cse_fpt.bin"
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help
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This file is the CSE input binary as released by Intel in a CSE kit.
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config CSE_DATA_FILE
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string "Name of CSE data file"
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default "cse_data.bin"
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help
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This file is the CSE data binary typically generated by Intel FIT tool.
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config CSE_PMCP_FILE
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string "Name of PMC file"
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default "pmc.bin"
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help
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This file is the PMC input binary as released by Intel in a CSE kit.
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config CSE_IOMP_FILE
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string "Name of IOM file"
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default "iom.bin"
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help
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This file is the IOM input binary as released by Intel in a CSE kit.
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config CSE_TBTP_FILE
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string "Name of TBT file"
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default "tbt.bin"
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help
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This file is the TBT input binary as released by Intel in a CSE kit.
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config CSE_NPHY_FILE
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string "Name of NPHY file"
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default "nphy.bin"
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help
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This file is the NPHY input binary as released by Intel in a CSE kit.
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config CSE_PCHC_FILE
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string "Name of PCHC file"
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default "pchc.bin"
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help
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This file is the PCHC input binary as released by Intel in a CSE kit.
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config CSE_IUNP_FILE
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string "Name of IUNIT file"
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default "iunit.bin"
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help
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This file is the PCHC input binary as released by Intel in a CSE kit.
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config CSE_BPDT_VERSION
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string
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help
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This config indicates the BPDT version used by CSE for a given SoC.
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endif
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@@ -6,6 +6,68 @@ smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c
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ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c
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ifeq ($(CONFIG_STITCH_ME_BIN),y)
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CSE_BP1_BIN := $(objcse)/cse_bp1.bin
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CSE_BP2_BIN := $(objcse)/cse_bp2.bin
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CSE_LAYOUT_BIN := $(objcse)/cse_layout.bin
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CSE_BPDT_VERSION := $(call strip_quotes,$(CONFIG_CSE_BPDT_VERSION))
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ifeq ($(CONFIG_CSE_BPDT_VERSION),)
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$(error "CONFIG_CSE_BPDT_VERSION is not set!")
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endif
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CSE_FPT_INPUT=$(call cse_input_path,$(CONFIG_CSE_FPT_FILE))
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CSE_DATA_INPUT=$(call cse_input_path,$(CONFIG_CSE_DATA_FILE))
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get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h)
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get_cse_region_offset=$(call int-subtract,$(call get_fmap_value,$(1)) $(CSE_LAYOUT_OFFSET))
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CSE_LAYOUT_OFFSET=$(call get_fmap_value,FMAP_SECTION_CSE_LAYOUT_START)
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CSE_BP1_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_RO_START)
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CSE_BP1_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_RO_SIZE)
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CSE_BP2_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_RW_START)
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CSE_BP2_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_RW_SIZE)
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CSE_DP_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_DATA_START)
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CSE_DP_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_DATA_SIZE)
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.PHONY: cse_inputs
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cse_inputs: $(cse_input_files)
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$(cse_decomp_files): $(CSE_FPT_INPUT) $(CSE_FPT)
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printf " DUMP $(@F)\n"
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$(CSE_FPT) $< dump -o $(objcse) -n $(@F) > /dev/null
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define cse_add_ingredient
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$(if $($(2)-file), \
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printf " CSEADD $(2) ($($(2)-file)) -> $(1)\n";
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$(CSE_SERGER) $@ add -n $(2) -f $($(2)-file) > /dev/null,
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printf " CSEADD $(2) (dummy) -> $(1)\n";
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$(CSE_SERGER) $@ add -n $(2) > /dev/null)
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endef
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$(objcse)/cse_%.bin: $(CSE_SERGER) cse_inputs $(cse_decomp_files)
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printf " CREATE $(@F) (version $(CSE_BPDT_VERSION))\n"
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$(CSE_SERGER) $@ create-bpdt -v $(CSE_BPDT_VERSION) > /dev/null
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$(foreach ingredient,$(cse_$*_ingredients),\
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$(call cse_add_ingredient,$(@F),$(ingredient));)
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$(CSE_LAYOUT_BIN): $(obj)/fmap_config.h $(CSE_SERGER)
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printf " CREATE $(@F) (version $(CSE_BPDT_VERSION))\n"
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$(CSE_SERGER) $@ create-layout -v $(CSE_BPDT_VERSION) \
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--bp1 $(CSE_BP1_OFFSET):$(CSE_BP1_SIZE) \
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--bp2 $(CSE_BP2_OFFSET):$(CSE_BP2_SIZE) \
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--dp $(CSE_DP_OFFSET):$(CSE_DP_SIZE) > /dev/null
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$(OBJ_ME_BIN): $(CSE_BP1_BIN) $(CSE_BP2_BIN) $(CSE_DATA_INPUT) $(CSE_LAYOUT_BIN)
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printf " CREATE $(@F)\n"
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dd if=$(CSE_LAYOUT_BIN) of=$@ bs=1 conv=notrunc 2> /dev/null
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dd if=$(CSE_BP1_BIN) of=$@ bs=1 conv=notrunc seek=$(CSE_BP1_OFFSET) 2> /dev/null
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dd if=$(CSE_BP2_BIN) of=$@ bs=1 conv=notrunc seek=$(CSE_BP2_OFFSET) 2> /dev/null
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dd if=$(CSE_DATA_INPUT) of=$@ bs=1 conv=notrunc seek=$(CSE_DP_OFFSET) 2> /dev/null
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endif
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ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y)
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ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"")
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