soc/intel/common/cse: Add support for stitching CSE components

This change adds support for allowing mainboards to stitch CSE
components during build time instead of adding a pre-built CSE
binary. Several Kconfig options are added to allow mainboard to
provide the file names for different CSE region components. This makes
use of the newly added cse_serger and cse_fpt tools to create
following partitions:
1. BP1 - RO
2. BP2 - RW
3. Layout

In addition to this, it accepts CSE data partition as an input using
Kconfig CSE_DATA_FILE. All these partitions are then assembled
together as per the following mainboard FMAP regions:
1. BP1(RO) : CSE_RO
2. BP2(RW) : CSE_RW
3. Layout  : CSE_LAYOUT
4. Data    : CSE_DATA

Finally, it generates the target $(OBJ_ME_BIN) which is used to put
together the binary in final coreboot.rom image.

Several helper functions are added to soc/intel/Makefile.inc to allow
SoCs to define which components use:
1. Decomposed files: Files decomposed from Intel release CSE binary in
FPT format.
2. Input files: Mainboard provided input files using corresponding
Kconfigs.
3. Dummy: Components that are required to have dummy entries in
BPDT header.

These helpers are added to soc/intel/Makefile.inc to ensure that the
functions are defined by the time the invocations are encountered in
SoC Makefile.inc.

BUG=b:189177580

Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Furquan Shaikh
2021-10-01 11:39:48 -07:00
parent 3959aa6351
commit 6ef863c5c4
3 changed files with 170 additions and 0 deletions

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@@ -0,0 +1,44 @@
ifeq ($(CONFIG_STITCH_ME_BIN),y)
objcse := $(obj)/cse
additional-dirs += $(objcse)
define cse_input_path
$(call strip_quotes,$(CONFIG_CSE_COMPONENTS_PATH))/$(call strip_quotes,$(1))
endef
define cse_add_dummy
$(eval cse_$(1)_ingredients+=$(2))
endef
define cse_add_dummy_to_bp1_bp2
$(call cse_add_dummy,bp1,$(1))
$(call cse_add_dummy,bp2,$(1))
endef
define cse_add_file
$(eval cse_$(3)_ingredients+=$(4))
$(eval file=$(2))
$(eval $(4)-file=$(file))
$(eval $(1)+=$(if $(filter $(file),$($(1))),,$(file)))
endef
define cse_add_decomp
$(call cse_add_file,cse_decomp_files,$(objcse)/$(2),$(1),$(2))
endef
define cse_add_decomp_to_bp1_bp2
$(call cse_add_decomp,bp1,$(1))
$(call cse_add_decomp,bp2,$(1))
endef
define cse_add_input
$(call cse_add_file,cse_input_files,$(call cse_input_path,$(CONFIG_CSE_$(2)_FILE)),$(1),$(2))
endef
define cse_add_input_to_bp1_bp2
$(call cse_add_input,bp1,$(1))
$(call cse_add_input,bp2,$(1))
endef
endif

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@@ -85,3 +85,67 @@ config SOC_INTEL_CSE_SET_EOP
This config ensures coreboot will send the CSE the End-of-POST message
just prior to loading the payload. This is a security feature so the
CSE will no longer respond to Pre-Boot commands.
if STITCH_ME_BIN
config CSE_COMPONENTS_PATH
string "Path to directory containing all CSE input components to stitch"
default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/firmware"
help
This is the file path containing all the input CSE component files.
These will be used by cse_serger tool to stitch CSE image.
config CSE_FPT_FILE
string "Name of CSE FPT file"
default "cse_fpt.bin"
help
This file is the CSE input binary as released by Intel in a CSE kit.
config CSE_DATA_FILE
string "Name of CSE data file"
default "cse_data.bin"
help
This file is the CSE data binary typically generated by Intel FIT tool.
config CSE_PMCP_FILE
string "Name of PMC file"
default "pmc.bin"
help
This file is the PMC input binary as released by Intel in a CSE kit.
config CSE_IOMP_FILE
string "Name of IOM file"
default "iom.bin"
help
This file is the IOM input binary as released by Intel in a CSE kit.
config CSE_TBTP_FILE
string "Name of TBT file"
default "tbt.bin"
help
This file is the TBT input binary as released by Intel in a CSE kit.
config CSE_NPHY_FILE
string "Name of NPHY file"
default "nphy.bin"
help
This file is the NPHY input binary as released by Intel in a CSE kit.
config CSE_PCHC_FILE
string "Name of PCHC file"
default "pchc.bin"
help
This file is the PCHC input binary as released by Intel in a CSE kit.
config CSE_IUNP_FILE
string "Name of IUNIT file"
default "iunit.bin"
help
This file is the PCHC input binary as released by Intel in a CSE kit.
config CSE_BPDT_VERSION
string
help
This config indicates the BPDT version used by CSE for a given SoC.
endif

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@@ -6,6 +6,68 @@ smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c
ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c
ifeq ($(CONFIG_STITCH_ME_BIN),y)
CSE_BP1_BIN := $(objcse)/cse_bp1.bin
CSE_BP2_BIN := $(objcse)/cse_bp2.bin
CSE_LAYOUT_BIN := $(objcse)/cse_layout.bin
CSE_BPDT_VERSION := $(call strip_quotes,$(CONFIG_CSE_BPDT_VERSION))
ifeq ($(CONFIG_CSE_BPDT_VERSION),)
$(error "CONFIG_CSE_BPDT_VERSION is not set!")
endif
CSE_FPT_INPUT=$(call cse_input_path,$(CONFIG_CSE_FPT_FILE))
CSE_DATA_INPUT=$(call cse_input_path,$(CONFIG_CSE_DATA_FILE))
get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h)
get_cse_region_offset=$(call int-subtract,$(call get_fmap_value,$(1)) $(CSE_LAYOUT_OFFSET))
CSE_LAYOUT_OFFSET=$(call get_fmap_value,FMAP_SECTION_CSE_LAYOUT_START)
CSE_BP1_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_RO_START)
CSE_BP1_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_RO_SIZE)
CSE_BP2_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_RW_START)
CSE_BP2_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_RW_SIZE)
CSE_DP_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_DATA_START)
CSE_DP_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_DATA_SIZE)
.PHONY: cse_inputs
cse_inputs: $(cse_input_files)
$(cse_decomp_files): $(CSE_FPT_INPUT) $(CSE_FPT)
printf " DUMP $(@F)\n"
$(CSE_FPT) $< dump -o $(objcse) -n $(@F) > /dev/null
define cse_add_ingredient
$(if $($(2)-file), \
printf " CSEADD $(2) ($($(2)-file)) -> $(1)\n";
$(CSE_SERGER) $@ add -n $(2) -f $($(2)-file) > /dev/null,
printf " CSEADD $(2) (dummy) -> $(1)\n";
$(CSE_SERGER) $@ add -n $(2) > /dev/null)
endef
$(objcse)/cse_%.bin: $(CSE_SERGER) cse_inputs $(cse_decomp_files)
printf " CREATE $(@F) (version $(CSE_BPDT_VERSION))\n"
$(CSE_SERGER) $@ create-bpdt -v $(CSE_BPDT_VERSION) > /dev/null
$(foreach ingredient,$(cse_$*_ingredients),\
$(call cse_add_ingredient,$(@F),$(ingredient));)
$(CSE_LAYOUT_BIN): $(obj)/fmap_config.h $(CSE_SERGER)
printf " CREATE $(@F) (version $(CSE_BPDT_VERSION))\n"
$(CSE_SERGER) $@ create-layout -v $(CSE_BPDT_VERSION) \
--bp1 $(CSE_BP1_OFFSET):$(CSE_BP1_SIZE) \
--bp2 $(CSE_BP2_OFFSET):$(CSE_BP2_SIZE) \
--dp $(CSE_DP_OFFSET):$(CSE_DP_SIZE) > /dev/null
$(OBJ_ME_BIN): $(CSE_BP1_BIN) $(CSE_BP2_BIN) $(CSE_DATA_INPUT) $(CSE_LAYOUT_BIN)
printf " CREATE $(@F)\n"
dd if=$(CSE_LAYOUT_BIN) of=$@ bs=1 conv=notrunc 2> /dev/null
dd if=$(CSE_BP1_BIN) of=$@ bs=1 conv=notrunc seek=$(CSE_BP1_OFFSET) 2> /dev/null
dd if=$(CSE_BP2_BIN) of=$@ bs=1 conv=notrunc seek=$(CSE_BP2_OFFSET) 2> /dev/null
dd if=$(CSE_DATA_INPUT) of=$@ bs=1 conv=notrunc seek=$(CSE_DP_OFFSET) 2> /dev/null
endif
ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y)
ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"")