soc/intel: Adapt crashlog IP to also support 64-bit
This patch extends the crashlog IP support beyond 32-bit mode to support Intel future generation SoCs, which may require crashlog support for 64-bit architectures. uintptr_t data type is used for Address pointers and void* for dereferencing BUG=b:346676856 TEST=Successfully built Meteor Lake (rex) and tested for google/rex0 and google/rex64 images. Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83106 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sowmya Aralguppe
Felix Held
parent
c0871f62f7
commit
702902d71f
@ -23,7 +23,7 @@ static pmc_crashlog_desc_table_t descriptor_table;
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static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap;
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static cpu_crashlog_discovery_table_t cpu_cl_disc_tab;
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u32 __weak cl_get_cpu_mb_int_addr(void)
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uintptr_t __weak cl_get_cpu_mb_int_addr(void)
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{
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return CRASHLOG_MAILBOX_INTF_ADDRESS;
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}
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@ -119,7 +119,7 @@ bool pmc_cl_discovery(void)
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return true;
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}
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u32 cl_get_cpu_bar_addr(void)
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uintptr_t cl_get_cpu_bar_addr(void)
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{
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u32 base_addr = 0;
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if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) {
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@ -137,7 +137,7 @@ u32 cl_get_cpu_bar_addr(void)
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}
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u32 cl_get_cpu_tmp_bar(void)
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uintptr_t cl_get_cpu_tmp_bar(void)
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{
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return sram_get_bar();
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}
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@ -189,8 +189,12 @@ static bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap)
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static bool cpu_cl_gen_discovery_table(void)
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{
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u32 bar_addr = 0, disc_tab_addr = 0;
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uintptr_t bar_addr = 0, disc_tab_addr = 0;
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bar_addr = cl_get_cpu_bar_addr();
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if (!bar_addr)
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return false;
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disc_tab_addr = bar_addr +
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cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset;
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memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t));
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@ -17,7 +17,7 @@ int __weak cl_get_pmc_record_size(void)
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return 0;
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}
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u32 __weak cl_get_cpu_bar_addr(void)
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uintptr_t __weak cl_get_cpu_bar_addr(void)
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{
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return 0;
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}
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@ -27,12 +27,12 @@ int __weak cl_get_ioe_record_size(void)
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return 0;
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}
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u32 __weak cl_get_cpu_tmp_bar(void)
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uintptr_t __weak cl_get_cpu_tmp_bar(void)
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{
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return 0;
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}
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u32 __weak cl_get_cpu_mb_int_addr(void)
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uintptr_t __weak cl_get_cpu_mb_int_addr(void)
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{
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return 0;
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}
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@ -106,13 +106,13 @@ cpu_crashlog_discovery_table_t __weak cl_get_cpu_discovery_table(void)
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return cpu_disc_tab;
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}
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int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr)
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int cpu_cl_poll_mailbox_ready(uintptr_t cl_mailbox_addr)
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{
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cpu_crashlog_mailbox_t cl_mailbox_interface;
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u16 stall_cnt = 0;
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do {
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cl_mailbox_interface.data = read32((u32 *)(uintptr_t)cl_mailbox_addr);
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cl_mailbox_interface.data = read32p(cl_mailbox_addr);
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udelay(CPU_CRASHLOG_WAIT_STALL);
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stall_cnt++;
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} while ((cl_mailbox_interface.fields.busy == 1)
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@ -130,7 +130,7 @@ int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr)
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int cpu_cl_mailbox_cmd(u8 cmd, u8 param)
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{
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cpu_crashlog_mailbox_t cl_mailbox_intf;
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u32 cl_base_addr;
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uintptr_t cl_base_addr;
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memset(&cl_mailbox_intf, 0, sizeof(cpu_crashlog_mailbox_t));
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@ -140,7 +140,7 @@ int cpu_cl_mailbox_cmd(u8 cmd, u8 param)
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cl_mailbox_intf.fields.param = param;
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cl_mailbox_intf.fields.busy = 1;
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write32((u32 *)(uintptr_t)(cl_base_addr + cl_get_cpu_mb_int_addr()),
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write32p((cl_base_addr + cl_get_cpu_mb_int_addr()),
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cl_mailbox_intf.data);
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cpu_cl_poll_mailbox_ready(cl_base_addr + cl_get_cpu_mb_int_addr());
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@ -163,12 +163,12 @@ void __weak cpu_cl_cleanup(void)
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/* empty implementation */
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}
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int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
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int pmc_cl_gen_descriptor_table(uintptr_t desc_table_addr,
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pmc_crashlog_desc_table_t *descriptor_table)
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{
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int total_data_size = 0;
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descriptor_table->numb_regions = read32((u32 *)(uintptr_t)desc_table_addr);
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printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%x\n",
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descriptor_table->numb_regions = read32p(desc_table_addr);
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printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%lx\n",
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descriptor_table->numb_regions, desc_table_addr);
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for (int i = 0; i < descriptor_table->numb_regions; i++) {
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if (i >= ARRAY_SIZE(descriptor_table->regions)) {
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@ -177,8 +177,8 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
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ARRAY_SIZE(descriptor_table->regions));
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break;
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}
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desc_table_addr += 4;
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descriptor_table->regions[i].data = read32((u32 *)(uintptr_t)(desc_table_addr));
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desc_table_addr += sizeof(u32);
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descriptor_table->regions[i].data = read32p(desc_table_addr);
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total_data_size += descriptor_table->regions[i].bits.size * sizeof(u32);
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printk(BIOS_DEBUG, "CL PMC desc table: region 0x%x has size 0x%x at offset 0x%x\n",
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i, descriptor_table->regions[i].bits.size,
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@ -280,49 +280,45 @@ bool discover_crashlog(void)
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return (cpu_cl_discovered || pmc_cl_discovered);
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}
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bool cl_copy_data_from_sram(u32 src_bar,
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u32 offset,
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u32 size,
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u32 *dest_addr,
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u32 buffer_index,
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bool pmc_sram)
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bool cl_copy_data_from_sram(uintptr_t src_bar, u32 offset, size_t size, u32 *dest_addr,
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u32 buffer_index, bool pmc_sram)
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{
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if (src_bar == 0) {
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printk(BIOS_ERR, "Invalid bar 0x%x and offset 0x%x for %s\n",
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printk(BIOS_ERR, "Invalid bar 0x%lx and offset 0x%x for %s\n",
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src_bar, offset, __func__);
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return false;
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}
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u32 src_addr = src_bar + offset;
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uintptr_t src_addr = src_bar + offset;
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u32 data = read32((u32 *)(uintptr_t)src_addr);
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u32 data = read32p(src_addr);
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/* First 32bits of the record must not be 0xdeadbeef */
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if (data == INVALID_CRASHLOG_RECORD) {
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printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x\n",
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printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%lx\n",
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data, offset, src_bar);
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return false;
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}
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/* PMC: copy if 1st DWORD in buffer is not zero and its 31st bit is not set */
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if (pmc_sram && !(data && !(data & BIT(31)))) {
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printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x"
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printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%lx"
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" of PMC SRAM.\n", data, offset, src_bar);
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return false;
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}
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/*CPU: don't copy if 1st DWORD in first buffer is zero */
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if (!pmc_sram && !data && (buffer_index == 0)) {
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printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x"
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printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%lx"
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" of telemetry SRAM.\n", data, offset, src_bar);
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return false;
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}
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u32 copied = 0;
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size_t copied = 0;
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while (copied < size) {
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/* DW by DW copy: byte access to PMC SRAM not allowed */
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*dest_addr = read32((u32 *)(uintptr_t)src_addr);
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*dest_addr = read32p(src_addr);
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dest_addr++;
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src_addr += 4;
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src_addr += sizeof(u32);
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copied++;
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}
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return true;
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@ -355,7 +351,7 @@ void free_cl_node(cl_node_t *node)
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void __weak cl_get_pmc_sram_data(cl_node_t *head)
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{
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u32 tmp_bar_addr = cl_get_cpu_tmp_bar();
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uintptr_t tmp_bar_addr = cl_get_cpu_tmp_bar();
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u32 pmc_crashLog_size = cl_get_pmc_record_size();
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cl_node_t *cl_cur = head;
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@ -476,9 +472,8 @@ void cl_get_cpu_sram_data(cl_node_t *head)
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}
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for (int i = 0 ; i < cpu_cl_disc_tab.header.fields.count ; i++) {
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u32 cpu_bar_addr = cl_get_cpu_bar_addr();
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uintptr_t cpu_bar_addr = cl_get_cpu_bar_addr();
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bool pmc_sram = false;
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if (!cpu_cl_disc_tab.buffers[i].fields.size) {
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continue;
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}
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@ -181,9 +181,9 @@ void free_cl_node(cl_node_t *node);
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int cl_get_cpu_record_size(void);
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int cl_get_pmc_record_size(void);
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int cl_get_ioe_record_size(void);
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u32 cl_get_cpu_bar_addr(void);
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u32 cl_get_cpu_tmp_bar(void);
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u32 cl_get_cpu_mb_int_addr(void);
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uintptr_t cl_get_cpu_bar_addr(void);
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uintptr_t cl_get_cpu_tmp_bar(void);
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uintptr_t cl_get_cpu_mb_int_addr(void);
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int cl_get_total_data_size(void);
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bool cl_pmc_sram_has_mmio_access(void);
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bool cl_ioe_sram_has_mmio_access(void);
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@ -201,13 +201,13 @@ void update_new_ioe_crashlog_size(u32 *pmc_crash_size);
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pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void);
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pmc_crashlog_desc_table_t cl_get_pmc_descriptor_table(void);
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cpu_crashlog_discovery_table_t cl_get_cpu_discovery_table(void);
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u32 cl_gen_cpu_bar_addr(void);
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int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr);
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uintptr_t cl_gen_cpu_bar_addr(void);
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int cpu_cl_poll_mailbox_ready(uintptr_t cl_mailbox_addr);
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int cpu_cl_mailbox_cmd(u8 cmd, u8 param);
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int cpu_cl_clear_data(void);
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void cpu_cl_rearm(void);
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void cpu_cl_cleanup(void);
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int pmc_cl_gen_descriptor_table(u32 desc_table_addr,
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int pmc_cl_gen_descriptor_table(uintptr_t desc_table_addr,
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pmc_crashlog_desc_table_t *descriptor_table);
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bool pmc_cl_discovery(void);
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bool cpu_cl_discovery(void);
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@ -215,12 +215,8 @@ int cl_pmc_re_arm_after_reset(void);
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int cl_pmc_clear(void);
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int cl_pmc_en_gen_on_all_reboot(void);
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bool discover_crashlog(void);
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bool cl_copy_data_from_sram(u32 src_bar,
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u32 offset,
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u32 size,
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u32 *dest_addr,
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u32 buffer_index,
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bool pmc_sram);
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bool cl_copy_data_from_sram(uintptr_t src_bar, u32 offset, size_t size, u32 *dest_addr,
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u32 buffer_index, bool pmc_sram);
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void collect_pmc_and_cpu_crashlog_from_srams(cl_node_t *head);
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static const EFI_GUID FW_ERR_SECTION_GUID = {
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0x81212a96, 0x09ed, 0x4996,
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@ -14,6 +14,7 @@
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#include <string.h>
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#define CONTROL_INTERFACE_OFFSET 0x5
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#define CRASHLOG_NODES_COUNT 0x2 /* Crashlog record of PUNIT & Uncore of SoC-N Die */
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#define CRASHLOG_PUNIT_STORAGE_OFF_MASK BIT(24)
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#define CRASHLOG_RE_ARM_STATUS_MASK BIT(25)
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#define CRASHLOG_CONSUMED_MASK BIT(31)
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@ -30,11 +31,11 @@ static pmc_ipc_discovery_buf_t discovery_buf;
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static pmc_crashlog_desc_table_t descriptor_table;
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static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap;
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static cpu_crashlog_discovery_table_t cpu_cl_disc_tab;
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static u32 disc_tab_addr;
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static uintptr_t disc_tab_addr;
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static u64 get_disc_tab_header(void)
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{
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return read64((void *)(uintptr_t)disc_tab_addr);
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return read64p(disc_tab_addr);
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}
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/* Get the SRAM BAR. */
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@ -62,7 +63,7 @@ static uintptr_t get_sram_bar(pci_devfn_t sram_devfn)
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return sram_bar;
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}
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static void configure_sram(const struct device *sram_dev, u32 base_addr)
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static void configure_sram(const struct device *sram_dev, uintptr_t base_addr)
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{
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pci_update_config16(sram_dev, PCI_COMMAND, ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY), 0);
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@ -73,8 +74,8 @@ static void configure_sram(const struct device *sram_dev, u32 base_addr)
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void cl_get_pmc_sram_data(cl_node_t *head)
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{
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u32 pmc_sram_base = cl_get_cpu_tmp_bar();
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u32 ioe_sram_base = get_sram_bar(PCI_DEVFN_IOE_SRAM);
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uintptr_t pmc_sram_base = cl_get_cpu_tmp_bar();
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uintptr_t ioe_sram_base = get_sram_bar(PCI_DEVFN_IOE_SRAM);
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u32 pmc_crashLog_size = cl_get_pmc_record_size();
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cl_node_t *cl_cur = head;
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@ -110,7 +111,7 @@ void cl_get_pmc_sram_data(cl_node_t *head)
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/* process crashlog records */
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for (int i = 0; i < descriptor_table.numb_regions + 1; i++) {
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u32 sram_base = 0;
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uintptr_t sram_base = 0;
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bool pmc_sram = true;
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printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n",
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i,
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@ -183,7 +184,7 @@ pmc_send_re_arm_after_reset:
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bool pmc_cl_discovery(void)
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{
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u32 bar_addr = 0, desc_table_addr = 0;
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uintptr_t bar_addr = 0, desc_table_addr = 0;
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const struct pmc_ipc_buffer req = { 0 };
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struct pmc_ipc_buffer res;
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@ -238,9 +239,9 @@ bool pmc_cl_discovery(void)
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return true;
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}
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u32 cl_get_cpu_bar_addr(void)
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uintptr_t cl_get_cpu_bar_addr(void)
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{
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u32 base_addr = 0;
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uintptr_t base_addr = 0;
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if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) {
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base_addr = pci_read_config32(PCI_DEV_TELEMETRY, PCI_BASE_ADDRESS_0) &
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~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
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@ -255,7 +256,7 @@ u32 cl_get_cpu_bar_addr(void)
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return base_addr;
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}
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u32 cl_get_cpu_tmp_bar(void)
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uintptr_t cl_get_cpu_tmp_bar(void)
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{
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return get_sram_bar(PCI_DEVFN_SRAM);
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}
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@ -331,37 +332,38 @@ static bool is_crashlog_data_valid(u32 dw0)
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static bool cpu_cl_gen_discovery_table(void)
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{
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u32 bar_addr = cl_get_cpu_bar_addr();
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uintptr_t bar_addr = cl_get_cpu_bar_addr();
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if (!bar_addr)
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return false;
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disc_tab_addr = bar_addr + get_disc_table_offset();
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u32 dw0 = read32((u32 *)(uintptr_t)disc_tab_addr);
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if (!is_crashlog_data_valid(dw0))
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return false;
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memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t));
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cpu_cl_disc_tab.header.data = get_disc_tab_header();
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printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer count: 0x%x\n",
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cpu_cl_disc_tab.header.fields.count);
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/* Check both 32 bit header data and status register for non-zero values */
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if ((!is_crashlog_data_valid(cpu_cl_disc_tab.header.data & 0xFFFFFFFF)) &&
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(!is_crashlog_data_valid((cpu_cl_disc_tab.header.data) >> 32)))
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return false;
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int cur_offset = 0;
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u32 cur_offset = 0;
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cpu_cl_disc_tab.header.fields.count = CRASHLOG_NODES_COUNT;
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printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer count: 0x%x\n",
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cpu_cl_disc_tab.header.fields.count);
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for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) {
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cur_offset = 8 + 24 * i;
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dw0 = read32((u32 *)(uintptr_t)disc_tab_addr + cur_offset);
|
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if (!is_crashlog_data_valid(dw0))
|
||||
u32 cl_buffer_size = read32p(disc_tab_addr + cur_offset + 4);
|
||||
/* Check for buffer size */
|
||||
if (!(is_crashlog_data_valid(cl_buffer_size)))
|
||||
continue;
|
||||
|
||||
u32 dw0 = read32p(disc_tab_addr + cur_offset);
|
||||
if (dw0 & CRASHLOG_CONSUMED_MASK) {
|
||||
printk(BIOS_DEBUG, "cpu crashlog records already consumed."
|
||||
"id: 0x%x dw0: 0x%x\n", i, dw0);
|
||||
break;
|
||||
}
|
||||
|
||||
cpu_cl_disc_tab.buffers[i].data = read64((void *)(uintptr_t)(disc_tab_addr + cur_offset));
|
||||
cpu_cl_disc_tab.buffers[i].data = read64p(disc_tab_addr + cur_offset);
|
||||
printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: "
|
||||
"0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size,
|
||||
cpu_cl_disc_tab.buffers[i].fields.offset);
|
||||
@ -411,7 +413,7 @@ int cl_get_total_data_size(void)
|
||||
return m_pmc_crashLog_size + m_cpu_crashLog_size;
|
||||
}
|
||||
|
||||
static u32 get_control_status_interface(void)
|
||||
static uintptr_t get_control_status_interface(void)
|
||||
{
|
||||
if (disc_tab_addr)
|
||||
return (disc_tab_addr + CONTROL_INTERFACE_OFFSET * sizeof(u32));
|
||||
@ -439,7 +441,7 @@ static bool wait_and_check(u32 bit_mask)
|
||||
|
||||
void cpu_cl_rearm(void)
|
||||
{
|
||||
u32 ctrl_sts_intfc_addr = get_control_status_interface();
|
||||
uintptr_t ctrl_sts_intfc_addr = get_control_status_interface();
|
||||
|
||||
if (!ctrl_sts_intfc_addr) {
|
||||
printk(BIOS_ERR, "CPU crashlog control and status interface address not valid\n");
|
||||
@ -450,7 +452,7 @@ void cpu_cl_rearm(void)
|
||||
cl_punit_control_interface_t punit_ctrl_intfc;
|
||||
memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
|
||||
punit_ctrl_intfc.fields.set_re_arm = 1;
|
||||
write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
|
||||
write32p(ctrl_sts_intfc_addr, punit_ctrl_intfc.data);
|
||||
|
||||
if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK))
|
||||
printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n");
|
||||
@ -461,7 +463,7 @@ void cpu_cl_rearm(void)
|
||||
void cpu_cl_cleanup(void)
|
||||
{
|
||||
/* Perform any SOC specific cleanup after reading the crashlog data from SRAM */
|
||||
u32 ctrl_sts_intfc_addr = get_control_status_interface();
|
||||
uintptr_t ctrl_sts_intfc_addr = get_control_status_interface();
|
||||
|
||||
if (!ctrl_sts_intfc_addr) {
|
||||
printk(BIOS_ERR, "CPU crashlog control and status interface address not valid\n");
|
||||
@ -480,7 +482,7 @@ void cpu_cl_cleanup(void)
|
||||
cl_punit_control_interface_t punit_ctrl_intfc;
|
||||
memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
|
||||
punit_ctrl_intfc.fields.set_storage_off = 1;
|
||||
write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
|
||||
write32p(ctrl_sts_intfc_addr, punit_ctrl_intfc.data);
|
||||
|
||||
if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK))
|
||||
printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n");
|
||||
|
||||
@ -21,7 +21,7 @@ static pmc_crashlog_desc_table_t descriptor_table;
|
||||
static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap;
|
||||
static cpu_crashlog_discovery_table_t cpu_cl_disc_tab;
|
||||
|
||||
u32 __weak cl_get_cpu_mb_int_addr(void)
|
||||
uintptr_t __weak cl_get_cpu_mb_int_addr(void)
|
||||
{
|
||||
return CRASHLOG_MAILBOX_INTF_ADDRESS;
|
||||
}
|
||||
@ -91,7 +91,7 @@ bool pmc_cl_discovery(void)
|
||||
return true;
|
||||
}
|
||||
|
||||
u32 cl_get_cpu_bar_addr(void)
|
||||
uintptr_t cl_get_cpu_bar_addr(void)
|
||||
{
|
||||
u32 base_addr = 0;
|
||||
if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) {
|
||||
@ -109,7 +109,7 @@ u32 cl_get_cpu_bar_addr(void)
|
||||
}
|
||||
|
||||
|
||||
u32 cl_get_cpu_tmp_bar(void)
|
||||
uintptr_t cl_get_cpu_tmp_bar(void)
|
||||
{
|
||||
return SPI_BASE_ADDRESS;
|
||||
}
|
||||
@ -161,8 +161,12 @@ static bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap)
|
||||
|
||||
static bool cpu_cl_gen_discovery_table(void)
|
||||
{
|
||||
u32 bar_addr = 0, disc_tab_addr = 0;
|
||||
uintptr_t bar_addr = 0, disc_tab_addr = 0;
|
||||
bar_addr = cl_get_cpu_bar_addr();
|
||||
|
||||
if (!bar_addr)
|
||||
return false;
|
||||
|
||||
disc_tab_addr = bar_addr +
|
||||
cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset;
|
||||
memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t));
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user