mb/google/rex: Simplify power limit configuration usage
This patch removes the deprecated PL_PERFORMANCE and PL_BASELINE configurations, relying instead on the refactored power limit flow. This flow allows for seamless overrides by the baseboard and/or by the variant board, if necessary. Specifically, this patch: - Removes PL_PERFORMANCE and PL_BASELINE configuration options from mainboard.c in the google/rex directory. - Relies on the baseboard_devtree_update() function, which is implemented by the respective baseboard, to handle power limit configuration. - Leverages the variant_devtree_update() function, which is a __weak implementation, to allow overrides by the variant directory. This simplification improves code readability and maintainability while maintaining the flexibility to handle power limit configurations as needed. Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79331 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
committed by
Matt DeVillier
parent
72d616c22c
commit
70770ebd36
@@ -239,17 +239,4 @@ config USE_PM_ACPI_TIMER
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config HAVE_SLP_S0_GATE
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def_bool n
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choice
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prompt "Choose desired processor power limits (PLs)"
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default PL_BASELINE if BOARD_GOOGLE_MODEL_SCREEBO
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default PL_PERFORMANCE
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config PL_PERFORMANCE
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bool "Performance: Maximum PLs for maximum performance"
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config PL_BASELINE
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bool "Baseline: Baseline PLs for balanced performance at lower power"
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endchoice
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endif # BOARD_GOOGLE_REX_COMMON
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@@ -10,7 +10,7 @@
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* pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
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* Following values are for performance config as per document #640982
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*/
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#if CONFIG(PL_PERFORMANCE)
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const struct cpu_tdp_power_limits performance_efficient_limits[] = {
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{
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.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
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@@ -52,49 +52,6 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
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.pl4_power = 64000
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},
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};
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#else
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const struct cpu_tdp_power_limits performance_efficient_limits[] = {
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{
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.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
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.cpu_tdp = 15,
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.pl1_min_power = 10000,
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.pl1_max_power = 15000,
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.pl2_min_power = 40000,
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.pl2_max_power = 40000,
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.pl4_power = 84000
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},
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{
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.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
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.cpu_tdp = 15,
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.pl1_min_power = 10000,
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.pl1_max_power = 15000,
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.pl2_min_power = 40000,
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.pl2_max_power = 40000,
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.pl4_power = 84000
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},
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};
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const struct cpu_tdp_power_limits power_optimized_limits[] = {
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{
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.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
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.cpu_tdp = 15,
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.pl1_min_power = 10000,
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.pl1_max_power = 15000,
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.pl2_min_power = 40000,
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.pl2_max_power = 40000,
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.pl4_power = 47000
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},
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{
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.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
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.cpu_tdp = 15,
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.pl1_min_power = 10000,
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.pl1_max_power = 15000,
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.pl2_min_power = 40000,
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.pl2_max_power = 40000,
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.pl4_power = 47000
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},
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};
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#endif
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void __weak variant_devtree_update(void)
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{
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