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mb/google/rex: Simplify power limit configuration usage

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This patch removes the deprecated PL_PERFORMANCE and PL_BASELINE
configurations, relying instead on the refactored power limit flow.

This flow allows for seamless overrides by the baseboard and/or by
the variant board, if necessary.

Specifically, this patch:

- Removes PL_PERFORMANCE and PL_BASELINE configuration options from
  mainboard.c in the google/rex directory.
- Relies on the baseboard_devtree_update() function, which is
  implemented by the respective baseboard, to handle power limit
  configuration.
- Leverages the variant_devtree_update() function, which is a
  __weak implementation, to allow overrides by the variant directory.

This simplification improves code readability and maintainability while
maintaining the flexibility to handle power limit configurations as
needed.

Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79331
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2023-11-29 01:05:58 +05:30
committed by Matt DeVillier
parent 72d616c22c
commit 70770ebd36
2 changed files with 1 additions and 57 deletions
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13
src/mainboard/google/rex/Kconfig
View File

@@ -239,17 +239,4 @@ config USE_PM_ACPI_TIMER
config HAVE_SLP_S0_GATE config HAVE_SLP_S0_GATE
def_bool n def_bool n
choice
prompt "Choose desired processor power limits (PLs)"
default PL_BASELINE if BOARD_GOOGLE_MODEL_SCREEBO
default PL_PERFORMANCE
config PL_PERFORMANCE
bool "Performance: Maximum PLs for maximum performance"
config PL_BASELINE
bool "Baseline: Baseline PLs for balanced performance at lower power"
endchoice
endif # BOARD_GOOGLE_REX_COMMON endif # BOARD_GOOGLE_REX_COMMON

45
src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
View File

@@ -10,7 +10,7 @@
* pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
* Following values are for performance config as per document #640982 * Following values are for performance config as per document #640982
*/ */
#if CONFIG(PL_PERFORMANCE)
const struct cpu_tdp_power_limits performance_efficient_limits[] = { const struct cpu_tdp_power_limits performance_efficient_limits[] = {
{ {
.mch_id = PCI_DID_INTEL_MTL_P_ID_2, .mch_id = PCI_DID_INTEL_MTL_P_ID_2,
@@ -52,49 +52,6 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
.pl4_power = 64000 .pl4_power = 64000
}, },
}; };
#else
const struct cpu_tdp_power_limits performance_efficient_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
.cpu_tdp = 15,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 40000,
.pl2_max_power = 40000,
.pl4_power = 84000
},
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
.cpu_tdp = 15,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 40000,
.pl2_max_power = 40000,
.pl4_power = 84000
},
};
const struct cpu_tdp_power_limits power_optimized_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
.cpu_tdp = 15,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 40000,
.pl2_max_power = 40000,
.pl4_power = 47000
},
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
.cpu_tdp = 15,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 40000,
.pl2_max_power = 40000,
.pl4_power = 47000
},
};
#endif
void __weak variant_devtree_update(void) void __weak variant_devtree_update(void)
{ {