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mb/google/brya/variants: Enable pch_hda_sdi_enable for trulo baseboard

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This patch enables pch_hda_sdi_enable for the trulo baseboard and
removes SDI lanes update from its variants.

BUG=b:350931954
TEST=Boot verified on google/craask and google/tivviks

Change-Id: I2e0f43b8fffb5e583089769d2c7446b476ce5d5d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83859
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Dinesh Gehlot 2024-08-10 12:47:33 +05:30 committed by Elyes Haouas
parent 76021a9205
commit 70e62188f4
3 changed files with 3 additions and 4 deletions
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3
src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
View File

@ -40,6 +40,9 @@ chip soc/intel/alderlake
register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2
register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3
# HD Audio
register "pch_hda_sdi_enable[0]" = "true"
register "pch_hda_sdi_enable[1]" = "true"
device domain 0 on
device ref igpu on end

2
src/mainboard/google/brya/variants/orisa/overridetree.cb
View File

@ -100,8 +100,6 @@ chip soc/intel/alderlake
# HD Audio
register "pch_hda_dsp_enable" = "1"
register "pch_hda_sdi_enable[0]" = "1"
register "pch_hda_sdi_enable[1]" = "1"
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"

2
src/mainboard/google/brya/variants/trulo/overridetree.cb
View File

@ -100,8 +100,6 @@ chip soc/intel/alderlake
# HD Audio
register "pch_hda_dsp_enable" = "1"
register "pch_hda_sdi_enable[0]" = "1"
register "pch_hda_sdi_enable[1]" = "1"
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"