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soc/intel/cmn/cse: Modify dependency on CSE lite configs

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Refactor CSE lite configs (specifically CSE sync related) to support
the alternative of sending CSE communication from the payload.

When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot
will skip initiating CSE sync operations and rely on the payload CSE
driver implementation.

The following configs are modified to ensure coreboot skips CSE
communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled:
- SOC_INTEL_CSE_LITE_PSR
- SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
- SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE
- SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE

BUG=b:305898363
TEST=Able to build google/rex.

Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Subrata Banik
2024-06-27 15:47:36 +05:30
parent d05fe9fd3c
commit 727bc08037
1 changed files with 4 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/intel/common/block/cse/Kconfig
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@@ -169,7 +169,7 @@ config SOC_INTEL_CSE_LITE_SKU
config SOC_INTEL_CSE_LITE_PSR
bool
default n
depends on SOC_INTEL_CSE_LITE_SKU
depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
help
Select this config if Platform Service Record(PSR) is supported by the platform. This
@@ -298,7 +298,7 @@ config SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
def_bool n
depends on SOC_INTEL_CSE_LITE_SKU
depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
help
Mainboard user to select this Kconfig in order to capture pre-cpu
reset boot performance telemetry data.
@@ -320,13 +320,14 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2
config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE
bool
default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
help
Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used.
config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
bool
default n
depends on !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
help
Use this option if CSE RW update needs to be triggered during RAMSTAGE.