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addw3: Set LAN clock as free running

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Change-Id: I9c3ab8b3af16ff23ebd6751b260ebea30021ec61
This commit is contained in:
Jeremy Soller
2023-03-17 09:10:17 -06:00
parent a2bbbc6769
commit 7285446cc7
1 changed files with 3 additions and 1 deletions
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src/mainboard/system76/rpl/variants/addw3/overridetree.cb
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@@ -50,11 +50,13 @@ chip soc/intel/alderlake
device ref pcie_rp3 on device ref pcie_rp3 on
# PCH RP#3 x1, Clock 13 (GLAN) # PCH RP#3 x1, Clock 13 (GLAN)
# Clock source is shared with LAN and hence marked as free running.
register "pch_pcie_rp[PCH_RP(3)]" = "{ register "pch_pcie_rp[PCH_RP(3)]" = "{
.clk_src = 13, .clk_src = 13,
.clk_req = 13, .clk_req = 13,
.flags = PCIE_RP_LTR | PCIE_RP_CLK_REQ_DETECT, .flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
}" }"
register "pcie_clk_config_flag[13]" = "PCIE_CLK_FREE_RUNNING"
device pci 00.0 on end device pci 00.0 on end
end end