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soc/intel/cannonlake: Allow PCIe root port #1 to use clockreq

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This commit is contained in:
Jeremy Soller
2020-08-19 11:35:27 -06:00
parent a9d462e94f
commit 729a256348
2 changed files with 4 additions and 0 deletions
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2
src/soc/intel/cannonlake/fsp_params.c
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@@ -468,6 +468,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
if (config->PcieClkSrcUsage[i] == 0) if (config->PcieClkSrcUsage[i] == 0)
config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
else if (config->PcieClkSrcUsage[i] == PCIE_CLK_RP0)
config->PcieClkSrcUsage[i] = 0;
} }
memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
sizeof(config->PcieClkSrcUsage)); sizeof(config->PcieClkSrcUsage));

2
src/soc/intel/cannonlake/include/soc/pch.h
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@@ -11,5 +11,7 @@
#define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_NOTUSED 0xFF
#define PCIE_CLK_LAN 0x70 #define PCIE_CLK_LAN 0x70
#define PCIE_CLK_FREE 0x80 #define PCIE_CLK_FREE 0x80
// Converted to 0, allows 0 to be notused
#define PCIE_CLK_RP0 0xFE
#endif #endif