mb/google/nissa/var/xivu: Disable CNVi WLAN/BT
Xivu uses PCIE WLAN, so disable the CNVi WLAN/BT. BUG=b:247120749 TEST=Boot to OS on xivu and check that WLAN/BT still works. Change-Id: I968d383278bd50268d899cff82067ceb7c3ba5ed Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Ben Kao <ben.kao@intel.com>
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@ -13,6 +13,18 @@ static const struct pad_config override_gpio_table[] = {
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PAD_NC(GPP_E20, NONE),
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/* E21 : DDP2_CTRLDATA ==> NC */
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PAD_NC(GPP_E21, NONE),
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/* F0 : CNV_BRI_DT ==> NC*/
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PAD_NC(GPP_F0, NONE),
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/* F1 : CNV_BRI_RSP ==> NC */
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PAD_NC(GPP_F1, NONE),
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/* F2 : CNV_RGI_DT ==> NC */
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PAD_NC(GPP_F2, NONE),
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/* F3 : CNV_RGI_RSP ==> NC */
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PAD_NC(GPP_F3, NONE),
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/* F4 : CNV_RF_RESET# ==> NC */
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PAD_NC(GPP_F4, NONE),
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/* F5 : CRF_XTAL_CLKREQ ==> NC */
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PAD_NC(GPP_F5, NONE),
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};
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/* Early pad configuration in bootblock */
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@ -35,8 +47,6 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */
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PAD_CFG_GPO(GPP_B11, 1, DEEP),
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/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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};
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@ -12,6 +12,9 @@ end
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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# Disable CNVi BT
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register "cnvi_bt_core" = "false"
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# SOC Aux orientation override:
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# This is a bitfield that corresponds to up to 4 TCSS ports.
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# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
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@ -209,6 +212,9 @@ chip soc/intel/alderlake
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device pci 00.0 on end
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end
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end
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device ref cnvi_wifi off end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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