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mb/google/nissa/var/xivu: Disable CNVi WLAN/BT

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Xivu uses PCIE WLAN, so disable the CNVi WLAN/BT.

BUG=b:247120749
TEST=Boot to OS on xivu and check that WLAN/BT still works.

Change-Id: I968d383278bd50268d899cff82067ceb7c3ba5ed
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
This commit is contained in:
Ian Feng
2022-09-26 17:13:13 +08:00
committed by Felix Held
parent 52a22fa7e6
commit 738a385b66
2 changed files with 18 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/mainboard/google/brya/variants/xivu/gpio.c
View File

@@ -13,6 +13,18 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E20, NONE),
/* E21 : DDP2_CTRLDATA ==> NC */
PAD_NC(GPP_E21, NONE),
/* F0 : CNV_BRI_DT ==> NC*/
PAD_NC(GPP_F0, NONE),
/* F1 : CNV_BRI_RSP ==> NC */
PAD_NC(GPP_F1, NONE),
/* F2 : CNV_RGI_DT ==> NC */
PAD_NC(GPP_F2, NONE),
/* F3 : CNV_RGI_RSP ==> NC */
PAD_NC(GPP_F3, NONE),
/* F4 : CNV_RF_RESET# ==> NC */
PAD_NC(GPP_F4, NONE),
/* F5 : CRF_XTAL_CLKREQ ==> NC */
PAD_NC(GPP_F5, NONE),
};
/* Early pad configuration in bootblock */
@@ -35,8 +47,6 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */
PAD_CFG_GPO(GPP_B11, 1, DEEP),
/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
PAD_CFG_GPO(GPP_H13, 1, DEEP),
};

6
src/mainboard/google/brya/variants/xivu/overridetree.cb
View File

@@ -12,6 +12,9 @@ end
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
# Disable CNVi BT
register "cnvi_bt_core" = "false"
# SOC Aux orientation override:
# This is a bitfield that corresponds to up to 4 TCSS ports.
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
@@ -209,6 +212,9 @@ chip soc/intel/alderlake
device pci 00.0 on end
end
end
device ref cnvi_wifi off end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]