amdfam10: Perform major include ".c" cleanup

Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)

This patch separates the build into separate .o modules
and links them accordingly.

Currently compiles and links all fam10 roms without
breaking other roms.

Both DDR2 and DDR3 have been completed

TESTED on REACTS: passes all boot tests for 2 boards
 ASUS KGPE-D16
 ASUS KFSN4-DRE

Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
 advansus/a785e-i
 asus/m5a88-v
 avalue/eax-785e

A followup patch may be required to fix the above boards.
See FIXME, XXX tags

Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>

src/cpu/amd/car/disable_cache_as_ram.c

@@ -19,6 +19,7 @@
  */
 
 #include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
 
 static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
 {

src/cpu/amd/car/post_cache_as_ram.c

@@ -17,11 +17,13 @@
  * GNU General Public License for more details.
  */
 #include <string.h>
+#include <console/console.h>
 #include <arch/stages.h>
 #include <arch/early_variables.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <cpu/amd/msr.h>
 #include <arch/acpi.h>
 #include <romstage_handoff.h>
 #include "cbmem.h"

src/cpu/amd/dualcore/dualcore.c

@@ -60,5 +60,4 @@ static inline void start_other_cores(void)
 			real_start_other_core(nodeid);
 		}
 	}
-
 }

src/cpu/amd/family_10h-family_15h/Makefile.inc

@@ -1,4 +1,7 @@
 romstage-y += ../../x86/mtrr/earlymtrr.c
+
+romstage-y += init_cpus.c
+
 ramstage-y += model_10xxx_init.c
 ramstage-y += processor_name.c
 

src/cpu/amd/family_10h-family_15h/fidvid.c

@@ -89,8 +89,7 @@ b.-  prep_fid_change(...)
 
  */
 
-#if CONFIG_SET_FIDVID
-
+#include <inttypes.h>
 #include <northbridge/amd/amdht/AsPsDefs.h>
 
 static inline void print_debug_fv(const char *str, u32 val)
@@ -601,7 +600,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev,
 	}
 }
 
-static void prep_fid_change(void)
+void prep_fid_change(void)
 {
 	u32 dword;
 	u32 nodes;
@@ -981,7 +980,7 @@ static void finalPstateChange(void)
 	set_pstate(0);
 }
 
-static void init_fidvid_stage2(u32 apicid, u32 nodeid)
+void init_fidvid_stage2(u32 apicid, u32 nodeid)
 {
 	msr_t msr;
 	pci_devfn_t dev;
@@ -1052,7 +1051,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp)
 #endif
 
 
-static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
+int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
 {
 #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
 	struct ap_apicid_st ap_apicidx;
@@ -1098,4 +1097,3 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
 
 	return 0;		// No FID/VID changes. Don't reset
 }
-#endif

src/cpu/amd/family_10h-family_15h/init_cpus.c

@@ -14,17 +14,17 @@
  * GNU General Public License for more details.
  */
 
-#include "cpu/amd/car/post_cache_as_ram.c"
-#include "defaults.h"
-#include <stdlib.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/mtrr.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
+#include "init_cpus.h"
+
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
+#include <pc80/mc146818rtc.h>
+
+#include <northbridge/amd/amdht/ht_wrapper.h>
 #include <northbridge/amd/amdht/AsPsDefs.h>
 #include <northbridge/amd/amdht/porting.h>
-
-#include <northbridge/amd/amdfam10/raminit_amdmct.c>
-#include <reset.h>
+#include <northbridge/amd/amdht/h3ncmn.h>
 
 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)
 #include <southbridge/amd/sb700/sb700.h>
@@ -34,12 +34,7 @@
 #include <southbridge/amd/sb800/sb800.h>
 #endif
 
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-static void prep_fid_change(void);
-static void init_fidvid_stage2(u32 apicid, u32 nodeid);
-#endif
-
-void cpuSetAMDMSR(uint8_t node_id);
+#include "cpu/amd/car/post_cache_as_ram.c"
 
 #if CONFIG_PCI_IO_CFG_EXT
 static void set_EnableCf8ExtCfg(void)
@@ -58,8 +53,6 @@ static void set_EnableCf8ExtCfg(void) { }
 // #define DEBUG_HT_SETUP 1
 // #define FAM10_AP_NODE_SEQUENTIAL_START 1
 
-typedef void (*process_ap_t) (u32 apicid, void *gp);
-
 uint32_t get_boot_apic_id(uint8_t node, uint32_t core) {
 	uint32_t ap_apicid;
 
@@ -369,7 +362,7 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid)
 	stop_this_cpu();
 }
 
-static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
+u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 {
 	uint32_t bsp_apicid = 0;
 	uint32_t apicid;
@@ -637,7 +630,7 @@ static void setup_remote_node(u8 node)
 #endif				/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
 //it is running on core0 of node0
-static void start_other_cores(uint32_t bsp_apicid)
+void start_other_cores(uint32_t bsp_apicid)
 {
 	u32 nodes;
 	u32 nodeid;
@@ -1855,7 +1848,7 @@ static void cpuInitializeMCA(void)
  * Do any additional post HT init
  *
  */
-static void finalize_node_setup(struct sys_info *sysinfo)
+void finalize_node_setup(struct sys_info *sysinfo)
 {
 	u8 i;
 	u8 nodes = get_nodes();
@@ -1886,4 +1879,6 @@ static void finalize_node_setup(struct sys_info *sysinfo)
 #endif
 }
 
-#include "fidvid.c"
+#if IS_ENABLED(CONFIG_SET_FIDVID)
+# include "fidvid.c"
+#endif

src/cpu/amd/family_10h-family_15h/init_cpus.h

@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef INIT_CPUS_H
+#define INIT_CPUS_H
+
+#include <stdlib.h>
+#include <console/console.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/amd/multicore.h>
+#include <reset.h>
+#include <northbridge/amd/amdfam10/raminit.h>
+#include "defaults.h"
+
+#define NODE_HT(x) NODE_PCI(x,0)
+#define NODE_MP(x) NODE_PCI(x,1)
+#define NODE_MC(x) NODE_PCI(x,3)
+#define NODE_LC(x) NODE_PCI(x,4)
+
+unsigned int get_sbdn(unsigned bus);
+void cpuSetAMDMSR(uint8_t node_id);
+
+typedef void (*process_ap_t) (u32 apicid, void *gp);
+
+uint32_t get_boot_apic_id(uint8_t node, uint32_t core);
+u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo);
+uint8_t set_apicid_cpuid_lo(void);
+void real_start_other_core(uint32_t nodeid, uint32_t cores);
+void finalize_node_setup(struct sys_info *sysinfo);
+uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2);
+void start_other_cores(uint32_t bsp_apicid);
+u32 get_core_num_in_bsp(u32 nodeid);
+
+void update_microcode(u32 cpu_deviceid);
+
+/* fidvid.c */
+void init_fidvid_stage2(u32 apicid, u32 nodeid);
+void prep_fid_change(void);
+int init_fidvid_bsp(u32 bsp_apicid, u32 nodes);
+
+#endif

src/cpu/amd/family_10h-family_15h/model_10xxx_init.c

@@ -35,21 +35,6 @@
 
 #define MCI_STATUS 0x401
 
-static inline uint8_t is_fam15h(void)
-{
-	uint8_t fam15h = 0;
-	uint32_t family;
-
-	family = cpuid_eax(0x80000001);
-	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
-	if (family >= 0x6f)
-		/* Family 15h or later */
-		fam15h = 1;
-
-	return fam15h;
-}
-
 static inline uint8_t is_gt_rev_d(void)
 {
 	uint8_t fam15h = 0;

src/cpu/amd/quadcore/quadcore.c

@@ -16,18 +16,13 @@
 
 #include <console/console.h>
 #include <pc80/mc146818rtc.h>
-#include <northbridge/amd/amdht/ht_wrapper.c>
 #if CONFIG_HAVE_OPTION_TABLE
 #include "option_table.h"
 #endif
 
 #include "cpu/amd/quadcore/quadcore_id.c"
 
-/* get_boot_apic_id and wait_cpu_state located in init_cpus.c */
-uint32_t get_boot_apic_id(uint8_t node, uint32_t core);
-uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2);
-
-static u32 get_core_num_in_bsp(u32 nodeid)
+u32 get_core_num_in_bsp(u32 nodeid)
 {
 	u32 dword;
 	if (is_fam15h()) {
@@ -46,7 +41,7 @@ static u32 get_core_num_in_bsp(u32 nodeid)
 	return dword;
 }
 
-static u8 set_apicid_cpuid_lo(void)
+u8 set_apicid_cpuid_lo(void)
 {
 	// set the NB_CFG[54]=1; why the OS will be happy with that ???
 	msr_t msr;
@@ -57,7 +52,7 @@ static u8 set_apicid_cpuid_lo(void)
 	return 1;
 }
 
-static void real_start_other_core(uint32_t nodeid, uint32_t cores)
+void real_start_other_core(uint32_t nodeid, uint32_t cores)
 {
 	ssize_t i;
 	uint32_t dword;