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amdfam10: Perform major include ".c" cleanup

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Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)

This patch separates the build into separate .o modules
and links them accordingly.

Currently compiles and links all fam10 roms without
breaking other roms.

Both DDR2 and DDR3 have been completed

TESTED on REACTS: passes all boot tests for 2 boards
 ASUS KGPE-D16
 ASUS KFSN4-DRE

Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
 advansus/a785e-i
 asus/m5a88-v
 avalue/eax-785e

A followup patch may be required to fix the above boards.
See FIXME, XXX tags

Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
This commit is contained in:
Damien Zammit 2016-11-28 00:29:10 +11:00 committed by Martin Roth
parent 6c20b65849
commit 75a3d1fb7c
146 changed files with 2633 additions and 1980 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/amd/car/disable_cache_as_ram.c
View File

@ -19,6 +19,7 @@
*/
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
{

2
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -17,11 +17,13 @@
* GNU General Public License for more details.
*/
#include <string.h>
#include <console/console.h>
#include <arch/stages.h>
#include <arch/early_variables.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/car.h>
#include <cpu/amd/msr.h>
#include <arch/acpi.h>
#include <romstage_handoff.h>
#include "cbmem.h"

1
src/cpu/amd/dualcore/dualcore.c
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@ -60,5 +60,4 @@ static inline void start_other_cores(void)
real_start_other_core(nodeid);
}
}
}

3
src/cpu/amd/family_10h-family_15h/Makefile.inc
View File

@ -1,4 +1,7 @@
romstage-y += ../../x86/mtrr/earlymtrr.c
romstage-y += init_cpus.c
ramstage-y += model_10xxx_init.c
ramstage-y += processor_name.c

10
src/cpu/amd/family_10h-family_15h/fidvid.c
View File

@ -89,8 +89,7 @@ b.- prep_fid_change(...)
*/
#if CONFIG_SET_FIDVID
#include <inttypes.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
static inline void print_debug_fv(const char *str, u32 val)
@ -601,7 +600,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev,
}
}
static void prep_fid_change(void)
void prep_fid_change(void)
{
u32 dword;
u32 nodes;
@ -981,7 +980,7 @@ static void finalPstateChange(void)
set_pstate(0);
}
static void init_fidvid_stage2(u32 apicid, u32 nodeid)
void init_fidvid_stage2(u32 apicid, u32 nodeid)
{
msr_t msr;
pci_devfn_t dev;
@ -1052,7 +1051,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp)
#endif
static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
{
#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
struct ap_apicid_st ap_apicidx;
@ -1098,4 +1097,3 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
return 0; // No FID/VID changes. Don't reset
}
#endif

37
src/cpu/amd/family_10h-family_15h/init_cpus.c
View File

@ -14,17 +14,17 @@
* GNU General Public License for more details.
*/
#include "cpu/amd/car/post_cache_as_ram.c"
#include "defaults.h"
#include <stdlib.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mtrr.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "init_cpus.h"
#if CONFIG_HAVE_OPTION_TABLE
#include "option_table.h"
#endif
#include <pc80/mc146818rtc.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
#include <northbridge/amd/amdht/porting.h>
#include <northbridge/amd/amdfam10/raminit_amdmct.c>
#include <reset.h>
#include <northbridge/amd/amdht/h3ncmn.h>
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)
#include <southbridge/amd/sb700/sb700.h>
@ -34,12 +34,7 @@
#include <southbridge/amd/sb800/sb800.h>
#endif
#if IS_ENABLED(CONFIG_SET_FIDVID)
static void prep_fid_change(void);
static void init_fidvid_stage2(u32 apicid, u32 nodeid);
#endif
void cpuSetAMDMSR(uint8_t node_id);
#include "cpu/amd/car/post_cache_as_ram.c"
#if CONFIG_PCI_IO_CFG_EXT
static void set_EnableCf8ExtCfg(void)
@ -58,8 +53,6 @@ static void set_EnableCf8ExtCfg(void) { }
// #define DEBUG_HT_SETUP 1
// #define FAM10_AP_NODE_SEQUENTIAL_START 1
typedef void (*process_ap_t) (u32 apicid, void *gp);
uint32_t get_boot_apic_id(uint8_t node, uint32_t core) {
uint32_t ap_apicid;
@ -369,7 +362,7 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid)
stop_this_cpu();
}
static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
{
uint32_t bsp_apicid = 0;
uint32_t apicid;
@ -637,7 +630,7 @@ static void setup_remote_node(u8 node)
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
//it is running on core0 of node0
static void start_other_cores(uint32_t bsp_apicid)
void start_other_cores(uint32_t bsp_apicid)
{
u32 nodes;
u32 nodeid;
@ -1855,7 +1848,7 @@ static void cpuInitializeMCA(void)
* Do any additional post HT init
*
*/
static void finalize_node_setup(struct sys_info *sysinfo)
void finalize_node_setup(struct sys_info *sysinfo)
{
u8 i;
u8 nodes = get_nodes();
@ -1886,4 +1879,6 @@ static void finalize_node_setup(struct sys_info *sysinfo)
#endif
}
#include "fidvid.c"
#if IS_ENABLED(CONFIG_SET_FIDVID)
# include "fidvid.c"
#endif

56
src/cpu/amd/family_10h-family_15h/init_cpus.h Normal file
View File

@ -0,0 +1,56 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef INIT_CPUS_H
#define INIT_CPUS_H
#include <stdlib.h>
#include <console/console.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/multicore.h>
#include <reset.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include "defaults.h"
#define NODE_HT(x) NODE_PCI(x,0)
#define NODE_MP(x) NODE_PCI(x,1)
#define NODE_MC(x) NODE_PCI(x,3)
#define NODE_LC(x) NODE_PCI(x,4)
unsigned int get_sbdn(unsigned bus);
void cpuSetAMDMSR(uint8_t node_id);
typedef void (*process_ap_t) (u32 apicid, void *gp);
uint32_t get_boot_apic_id(uint8_t node, uint32_t core);
u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo);
uint8_t set_apicid_cpuid_lo(void);
void real_start_other_core(uint32_t nodeid, uint32_t cores);
void finalize_node_setup(struct sys_info *sysinfo);
uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2);
void start_other_cores(uint32_t bsp_apicid);
u32 get_core_num_in_bsp(u32 nodeid);
void update_microcode(u32 cpu_deviceid);
/* fidvid.c */
void init_fidvid_stage2(u32 apicid, u32 nodeid);
void prep_fid_change(void);
int init_fidvid_bsp(u32 bsp_apicid, u32 nodes);
#endif

15
src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
View File

@ -35,21 +35,6 @@
#define MCI_STATUS 0x401
static inline uint8_t is_fam15h(void)
{
uint8_t fam15h = 0;
uint32_t family;
family = cpuid_eax(0x80000001);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
if (family >= 0x6f)
/* Family 15h or later */
fam15h = 1;
return fam15h;
}
static inline uint8_t is_gt_rev_d(void)
{
uint8_t fam15h = 0;

11
src/cpu/amd/quadcore/quadcore.c
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@ -16,18 +16,13 @@
#include <console/console.h>
#include <pc80/mc146818rtc.h>
#include <northbridge/amd/amdht/ht_wrapper.c>
#if CONFIG_HAVE_OPTION_TABLE
#include "option_table.h"
#endif
#include "cpu/amd/quadcore/quadcore_id.c"
/* get_boot_apic_id and wait_cpu_state located in init_cpus.c */
uint32_t get_boot_apic_id(uint8_t node, uint32_t core);
uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2);
static u32 get_core_num_in_bsp(u32 nodeid)
u32 get_core_num_in_bsp(u32 nodeid)
{
u32 dword;
if (is_fam15h()) {
@ -46,7 +41,7 @@ static u32 get_core_num_in_bsp(u32 nodeid)
return dword;
}
static u8 set_apicid_cpuid_lo(void)
u8 set_apicid_cpuid_lo(void)
{
// set the NB_CFG[54]=1; why the OS will be happy with that ???
msr_t msr;
@ -57,7 +52,7 @@ static u8 set_apicid_cpuid_lo(void)
return 1;
}
static void real_start_other_core(uint32_t nodeid, uint32_t cores)
void real_start_other_core(uint32_t nodeid, uint32_t cores)
{
ssize_t i;
uint32_t dword;

3
src/mainboard/advansus/a785e-i/Kconfig
View File

@ -7,10 +7,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select DIMM_REGISTERED
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_AMD_RS780
select SOUTHBRIDGE_AMD_CIMX_SB800
select SOUTHBRIDGE_AMD_SB800
select SUPERIO_WINBOND_W83627HF #COM1, COM2
#select SUPERIO_FINTEK_F81216AD #COM3, COM4
select SB_SUPERIO_HWM
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY

16
src/mainboard/advansus/a785e-i/Makefile.inc
View File

@ -1,16 +0,0 @@
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
AGESA_INC := -I$(AGESA_ROOT)/ \
-I$(AGESA_ROOT)/../common \
-I$(AGESA_ROOT)/Include \
-I$(AGESA_ROOT)/Proc/IDS/ \
-I$(AGESA_ROOT)/Proc/CPU/ \
-I$(AGESA_ROOT)/Proc/CPU/Family
CFLAGS_common += $(AGESA_INC)
endif

8
src/mainboard/advansus/a785e-i/mainboard.c
View File

@ -20,8 +20,6 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "SBPLATFORM.h"
u8 is_dev3_present(void);
void set_pcie_dereset(void);
@ -34,14 +32,14 @@ void enable_int_gfx(void)
volatile u8 *gpio_reg;
/* make sure the Acpi MMIO(fed80000) is accessible */
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
// XXX Redo this RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;

5
src/mainboard/advansus/a785e-i/mptable.c
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@ -20,7 +20,6 @@
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
#include <SBPLATFORM.h>
extern int bus_isa;
extern u8 bus_rs780[11];
@ -42,7 +41,7 @@ u8 intr_data[] = {
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
u32 dword;
u32 dword = 0;
u8 byte;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -56,7 +55,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
// XXX Redo this: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);

48
src/mainboard/advansus/a785e-i/romstage.c
View File

@ -15,7 +15,6 @@
#define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */
/* used by incoherent_ht */
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@ -30,43 +29,43 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <cpu/amd/car.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <southbridge/amd/sb800/smbus.h>
#include <southbridge/amd/sb800/sb800.h>
#include "southbridge/amd/rs780/early_setup.c"
#include <sb_cimx.h>
#include <SBPLATFORM.h> /* SB OEM constants */
#include <southbridge/amd/cimx/sb800/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/amd/sb800/early_setup.c"
#include <arch/early_variables.h>
#include <cbmem.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "spd.h"
#include <reset.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "spd.h"
#include <reset.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
@ -85,7 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
/* enable port80 decoding and southbridge poweron init */
sb_Poweron_Init();
sb800_lpc_init();
sb800_pci_port80();
}
post_code(0x30);
@ -156,12 +156,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
rs780_early_setup();
sb800_early_setup();
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
@ -203,6 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */

39
src/mainboard/amd/bimini_fam10/romstage.c
View File

@ -29,38 +29,37 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb800/smbus.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb800/early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
void activate_spd_rom(const struct mem_controller *ctrl)
{
}
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

4
src/mainboard/amd/mahogany/romstage.c
View File

@ -31,11 +31,12 @@
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
unsigned get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
@ -46,6 +47,7 @@ static inline int spd_read_byte(u32 device, u32 address)
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "southbridge/amd/rs780/early_setup.c"
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"

33
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -31,41 +31,40 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/amd/rs780/early_setup.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
static int spd_read_byte(u32 device, u32 address)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
void activate_spd_rom(const struct mem_controller *ctrl) { }
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

4
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -31,10 +31,11 @@
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
unsigned get_sbdn(unsigned bus);
static void memreset_setup(void)
{
/* GPIO on amd8111 to enable MEMRST ???? */
@ -63,6 +64,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/amd/amd8111/early_ctrl.c"
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

34
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -29,23 +29,31 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/amd/amd8111/early_smbus.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <spd.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <cpu/amd/car.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/amd/amd8111/early_smbus.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static void memreset_setup(void)
{
/* GPIO on amd8111 to enable MEMRST ???? */
@ -53,7 +61,7 @@ static void memreset_setup(void)
outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
int ret,i;
@ -69,21 +77,11 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
static int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static const u8 spd_addr[] = {
/* first node */
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,

35
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -29,41 +29,40 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
#include "southbridge/amd/rs780/early_setup.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static int spd_read_byte(u32 device, u32 address)
void activate_spd_rom(const struct mem_controller *ctrl) { }
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

4
src/mainboard/asrock/939a785gmh/romstage.c
View File

@ -32,7 +32,6 @@
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
@ -40,6 +39,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
unsigned get_sbdn(unsigned bus);
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -48,6 +49,7 @@ static inline int spd_read_byte(u32 device, u32 address)
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "southbridge/amd/rs780/early_setup.c"
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"

34
src/mainboard/asus/kcma-d8/romstage.c
View File

@ -30,43 +30,37 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
#include <cpu/x86/bist.h>
#include <smp/spinlock.h>
// #include "northbridge/amd/amdk8/incoherent_ht.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include <southbridge/amd/sr5650/sr5650.h>
#include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
static void activate_spd_rom(const struct mem_controller *ctrl);
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static inline int spd_read_byte(unsigned device, unsigned address)
inline int spd_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
/*
* ASUS KCMA-D8 specific SPD enable/disable magic.
*
@ -108,7 +102,7 @@ static const uint8_t spd_addr_fam10[] = {
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
};
static void activate_spd_rom(const struct mem_controller *ctrl) {
void activate_spd_rom(const struct mem_controller *ctrl) {
printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
if (ctrl->node_id == 0) {
printk(BIOS_DEBUG, "enable_spd_node0()\n");

44
src/mainboard/asus/kfsn4-dre/romstage.c
View File

@ -20,8 +20,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 1
unsigned int get_sbdn(unsigned bus);
#include <stdint.h>
#include <string.h>
#include <reset.h>
@ -34,47 +32,41 @@ unsigned int get_sbdn(unsigned bus);
#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cbmem.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/nvidia/ck804/early_smbus.h"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/amd/car.h>
#include <southbridge/nvidia/ck804/early_smbus.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627thg/w83627thg.h>
#include <cpu/x86/bist.h>
// #include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl);
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
#define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/
#include <southbridge/nvidia/ck804/early_setup_ss.h>
#include "southbridge/nvidia/ck804/early_setup_car.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
@ -182,7 +174,7 @@ static const uint8_t spd_addr[] = {
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
};
static void activate_spd_rom(const struct mem_controller *ctrl) {
void activate_spd_rom(const struct mem_controller *ctrl) {
printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
if (ctrl->node_id == 0) {
printk(BIOS_DEBUG, "enable_spd_node0()\n");

35
src/mainboard/asus/kgpe-d16/romstage.c
View File

@ -30,43 +30,37 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
#include <smp/spinlock.h>
// #include "northbridge/amd/amdk8/incoherent_ht.c"
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include <southbridge/amd/sr5650/sr5650.h>
#include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
static void activate_spd_rom(const struct mem_controller *ctrl);
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static inline int spd_read_byte(unsigned device, unsigned address)
int spd_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_AUX_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
/*
* ASUS KGPE-D16 specific SPD enable/disable magic.
*
@ -116,9 +110,8 @@ static const uint8_t spd_addr_fam10[] = {
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
};
static void activate_spd_rom(const struct mem_controller *ctrl) {
void activate_spd_rom(const struct mem_controller *ctrl) {
struct sys_info *sysinfo = &sysinfo_car;
printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
if (ctrl->node_id == 0) {
printk(BIOS_DEBUG, "enable_spd_node0()\n");

15
src/mainboard/asus/m2n-e/romstage.c
View File

@ -38,11 +38,23 @@
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
unsigned get_sbdn(unsigned bus);
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) {}
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
@ -51,6 +63,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

37
src/mainboard/asus/m4a78-em/romstage.c
View File

@ -17,7 +17,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@ -31,43 +30,41 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
#include "southbridge/amd/rs780/early_setup.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static int spd_read_byte(u32 device, u32 address)
void activate_spd_rom(const struct mem_controller *ctrl) { }
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;

36
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -31,43 +31,41 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
#include "southbridge/amd/rs780/early_setup.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static int spd_read_byte(u32 device, u32 address)
void activate_spd_rom(const struct mem_controller *ctrl) { }
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;

2
src/mainboard/asus/m5a88-v/Kconfig
View File

@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select DIMM_REGISTERED
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_AMD_RS780
select SOUTHBRIDGE_AMD_CIMX_SB800
select SOUTHBRIDGE_AMD_SB800
select SUPERIO_ITE_IT8721F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE

16
src/mainboard/asus/m5a88-v/Makefile.inc
View File

@ -1,16 +0,0 @@
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
AGESA_INC := -I$(AGESA_ROOT)/ \
-I$(AGESA_ROOT)/../common \
-I$(AGESA_ROOT)/Include \
-I$(AGESA_ROOT)/Proc/IDS/ \
-I$(AGESA_ROOT)/Proc/CPU/ \
-I$(AGESA_ROOT)/Proc/CPU/Family
CFLAGS_common += $(AGESA_INC)
endif

8
src/mainboard/asus/m5a88-v/mainboard.c
View File

@ -20,8 +20,6 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "SBPLATFORM.h"
u8 is_dev3_present(void);
void set_pcie_dereset(void);
@ -34,14 +32,14 @@ void enable_int_gfx(void)
volatile u8 *gpio_reg;
/* make sure the MMIO(fed80000) is accessible */
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
// FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;

5
src/mainboard/asus/m5a88-v/mptable.c
View File

@ -20,7 +20,6 @@
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
#include <SBPLATFORM.h>
extern int bus_isa;
extern u8 bus_rs780[11];
@ -42,7 +41,7 @@ u8 intr_data[] = {
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
u32 dword;
u32 dword = 0;
u8 byte;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -56,7 +55,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
// FIXME: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);

49
src/mainboard/asus/m5a88-v/romstage.c
View File

@ -17,7 +17,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@ -32,42 +31,43 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8721f/it8721f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb800/smbus.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/amd/rs780/early_setup.c"
#include <sb_cimx.h>
#include <SBPLATFORM.h> /* SB OEM constants */
#include <southbridge/amd/cimx/sb800/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/amd/sb800/early_setup.c"
#include "spd.h"
#include <reset.h>
static void activate_spd_rom(const struct mem_controller *ctrl)
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "spd.h"
#include <reset.h>
#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
@ -86,7 +86,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
//enable port80 decoding and southbridge poweron init
sb_Poweron_Init();
sb800_lpc_init();
sb800_pci_port80();
}
post_code(0x30);
@ -157,12 +158,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
rs780_early_setup();
sb800_early_setup();
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
if (!warm_reset_detect(0)) { // BSP is node 0
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
@ -218,6 +222,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.

3
src/mainboard/avalue/eax-785e/Kconfig
View File

@ -7,10 +7,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select DIMM_REGISTERED
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_AMD_RS780
select SOUTHBRIDGE_AMD_CIMX_SB800
select SOUTHBRIDGE_AMD_SB800
select SUPERIO_WINBOND_W83627HF #COM1, COM2
#select SUPERIO_FINTEK_F81216AD #COM3, COM4
select SB_SUPERIO_HWM
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY

16
src/mainboard/avalue/eax-785e/Makefile.inc
View File

@ -1,16 +0,0 @@
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
AGESA_INC := -I$(AGESA_ROOT)/ \
-I$(AGESA_ROOT)/../common \
-I$(AGESA_ROOT)/Include \
-I$(AGESA_ROOT)/Proc/IDS/ \
-I$(AGESA_ROOT)/Proc/CPU/ \
-I$(AGESA_ROOT)/Proc/CPU/Family
CFLAGS_common += $(AGESA_INC)
endif

8
src/mainboard/avalue/eax-785e/mainboard.c
View File

@ -20,8 +20,6 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "SBPLATFORM.h"
u8 is_dev3_present(void);
void set_pcie_dereset(void);
@ -34,14 +32,14 @@ void enable_int_gfx(void)
volatile u8 *gpio_reg;
/* make sure the Acpi MMIO(fed80000) is accessible */
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
// FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;

5
src/mainboard/avalue/eax-785e/mptable.c
View File

@ -19,7 +19,6 @@
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
#include <SBPLATFORM.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern int bus_isa;
@ -42,7 +41,7 @@ u8 intr_data[] = {
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
u32 dword;
u32 dword = 0;
u8 byte;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -56,7 +55,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
// FIXME: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);

47
src/mainboard/avalue/eax-785e/romstage.c
View File

@ -15,7 +15,6 @@
#define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */
/* used by incoherent_ht */
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@ -30,44 +29,43 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb800/smbus.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "spd.h"
#include <reset.h>
#include "southbridge/amd/rs780/early_setup.c"
#include <sb_cimx.h>
#include <SBPLATFORM.h> /* SB OEM constants */
#include <southbridge/amd/cimx/sb800/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/amd/sb800/early_setup.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "spd.h"
#include <reset.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
@ -86,7 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
/*enable port80 decoding and southbridge poweron init */
sb_Poweron_Init();
sb800_lpc_init();
sb800_pci_port80();
}
post_code(0x30);
@ -157,12 +156,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
rs780_early_setup();
sb800_early_setup();
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
@ -204,6 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
rs780_before_pci_init();
sb800_before_pci_init();
post_code(0x42);
post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */

3
src/mainboard/broadcom/blast/romstage.c
View File

@ -17,11 +17,11 @@
#include <superio/nsc/pc87417/pc87417.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/broadcom/bcm5785/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
unsigned get_sbdn(unsigned bus);
static void memreset_setup(void) { }
static void memreset(int controllers, const struct mem_controller *ctrl) { }
@ -37,6 +37,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/broadcom/bcm5785/early_setup.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"

15
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -36,11 +36,23 @@
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
unsigned get_sbdn(unsigned bus);
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -57,6 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <southbridge/nvidia/mcp55/early_setup_ss.h>
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include <northbridge/amd/amdk8/f.h>

36
src/mainboard/gigabyte/ma785gm/romstage.c
View File

@ -27,43 +27,41 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
#include "southbridge/amd/rs780/early_setup.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static int spd_read_byte(u32 device, u32 address)
void activate_spd_rom(const struct mem_controller *ctrl) { }
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;

36
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -27,43 +27,41 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include <spd.h>
#include "southbridge/amd/rs780/early_setup.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static int spd_read_byte(u32 device, u32 address)
void activate_spd_rom(const struct mem_controller *ctrl) { }
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;

37
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -17,7 +17,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@ -31,43 +30,41 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/amd/rs780/early_setup.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static int spd_read_byte(u32 device, u32 address)
void activate_spd_rom(const struct mem_controller *ctrl) { }
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;

4
src/mainboard/hp/dl145_g1/romstage.c
View File

@ -20,10 +20,11 @@
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/x86/bist.h>
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
unsigned get_sbdn(unsigned bus);
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@ -79,6 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/amd/amd8111/early_ctrl.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "resourcemap.c"

4
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -41,11 +41,12 @@
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/broadcom/bcm5785/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
unsigned get_sbdn(unsigned bus);
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
@ -62,6 +63,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/broadcom/bcm5785/early_setup.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

31
src/mainboard/hp/dl165_g6_fam10/romstage.c
View File

@ -35,24 +35,32 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/broadcom/bcm5785/early_smbus.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <spd.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <superio/serverengines/pilot/pilot.h>
#include <superio/nsc/pc87417/pc87417.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <cpu/amd/car.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/broadcom/bcm5785/early_smbus.c"
#include "southbridge/broadcom/bcm5785/early_setup.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
inline void activate_spd_rom(const struct mem_controller *ctrl)
{
u8 val;
outb(0x3d, 0x0cd6);
@ -63,20 +71,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7);
}
static inline int spd_read_byte(unsigned device, unsigned address)
inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static const u8 spd_addr[] = {
// switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr
//first node

37
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -17,7 +17,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@ -31,42 +30,40 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71859/f71859.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/amd/rs780/early_setup.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static int spd_read_byte(u32 device, u32 address)
void activate_spd_rom(const struct mem_controller *ctrl) { }
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;

4
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -16,10 +16,11 @@
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/amd8111/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
unsigned get_sbdn(unsigned bus);
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
@ -54,6 +55,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/amd/amd8111/early_ctrl.c"
#include <northbridge/amd/amdk8/amdk8.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

37
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -18,7 +18,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@ -32,21 +31,26 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71863fg/f71863fg.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/amd/rs780/early_setup.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#if CONFIG_TTYS0_BASE == 0x2f8
#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP2)
@ -54,24 +58,17 @@
#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
#endif
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static int spd_read_byte(u32 device, u32 address)
void activate_spd_rom(const struct mem_controller *ctrl) { }
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;

15
src/mainboard/msi/ms7260/romstage.c
View File

@ -38,10 +38,22 @@
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
unsigned get_sbdn(unsigned bus);
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) {}
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
@ -50,6 +62,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

4
src/mainboard/msi/ms9185/romstage.c
View File

@ -39,11 +39,12 @@
#include <superio/nsc/pc87417/pc87417.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/broadcom/bcm5785/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
unsigned get_sbdn(unsigned bus);
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
@ -60,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/broadcom/bcm5785/early_setup.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

15
src/mainboard/msi/ms9282/romstage.c
View File

@ -39,10 +39,22 @@
#include <spd.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <device/pci_ids.h>
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
unsigned get_sbdn(unsigned bus);
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
@ -59,6 +71,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

43
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -30,33 +30,46 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/nvidia/mcp55/early_smbus.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <cpu/amd/car.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/nvidia/mcp55/early_smbus.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static inline int spd_read_byte(unsigned device, unsigned address)
void activate_spd_rom(const struct mem_controller *ctrl) { }
inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
@ -68,10 +81,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <southbridge/nvidia/mcp55/early_setup_ss.h>
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
{

15
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -37,10 +37,22 @@
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
unsigned get_sbdn(unsigned bus);
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -49,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

15
src/mainboard/sunw/ultra40m2/romstage.c
View File

@ -36,10 +36,22 @@
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1)
unsigned get_sbdn(unsigned bus);
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -48,6 +60,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

15
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -34,11 +34,23 @@
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
unsigned get_sbdn(unsigned bus);
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
@ -58,6 +70,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

15
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -37,11 +37,23 @@
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
unsigned get_sbdn(unsigned bus);
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -50,6 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

54
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -30,40 +30,50 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <cpu/amd/car.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <southbridge/nvidia/mcp55/early_setup_ss.h>
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
void activate_spd_rom(const struct mem_controller *ctrl) { }
inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void sio_setup(void)
{

45
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -30,47 +30,56 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <cpu/amd/car.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <southbridge/nvidia/mcp55/early_setup_ss.h>
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
#define SMBUS_SWITCH1 0x70
#define SMBUS_SWITCH2 0x72
static inline void activate_spd_rom(const struct mem_controller *ctrl)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
inline void activate_spd_rom(const struct mem_controller *ctrl)
{
smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
}
static inline int spd_read_byte(unsigned device, unsigned address)
inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <southbridge/nvidia/mcp55/early_setup_ss.h>
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include <cpu/amd/microcode.h>
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void sio_setup(void)
{

34
src/mainboard/supermicro/h8scm_fam10/romstage.c
View File

@ -17,7 +17,6 @@
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@ -31,40 +30,39 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include <southbridge/amd/sr5650/sr5650.h>
#include <superio/nuvoton/wpcm450/wpcm450.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
static void activate_spd_rom(const struct mem_controller *ctrl)
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static int spd_read_byte(u32 device, u32 address)
int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;

15
src/mainboard/tyan/s2912/romstage.c
View File

@ -37,10 +37,22 @@
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
unsigned get_sbdn(unsigned bus);
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@ -49,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"

43
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -30,34 +30,36 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/nvidia/mcp55/early_smbus.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <cpu/amd/car.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdht/ht_wrapper.h>
#include <cpu/amd/family_10h-family_15h/init_cpus.h>
#include <arch/early_variables.h>
#include <cbmem.h>
#include "southbridge/nvidia/mcp55/early_smbus.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned device, unsigned address);
extern struct sys_info sysinfo_car;
static inline int spd_read_byte(unsigned device, unsigned address)
void activate_spd_rom(const struct mem_controller *ctrl) { }
inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
@ -68,10 +70,17 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <southbridge/nvidia/mcp55/early_setup_ss.h>
#include "southbridge/nvidia/mcp55/early_setup_car.c"
#include <cpu/amd/microcode.h>
#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static void sio_setup(void)
{

21
src/northbridge/amd/amdfam10/Makefile.inc
View File

@ -1,18 +1,19 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y)
ramstage-y += northbridge.c
ramstage-y += misc_control.c
ramstage-y += link_control.c
ramstage-y += nb_control.c
romstage-y += amdfam10_util.c
ramstage-y += amdfam10_util.c
subdirs-y += ../amdht
subdirs-y += ../amdmct/wrappers
subdirs-$(CONFIG_DIMM_DDR3) += ../amdmct/mct_ddr3
subdirs-$(CONFIG_DIMM_DDR2) += ../amdmct/mct
ramstage-y += ht_config.c
# Generic ROMSTAGE stuff
romstage-y += reset_test.c debug.c setup_resource_map.c raminit_sysinfo_in_ram.c
romstage-y += raminit_amdmct.c pci.c early_ht.c amdfam10_util.c
# RAMSTAGE
ramstage-y += northbridge.c misc_control.c link_control.c nb_control.c
ramstage-y += amdfam10_util.c ht_config.c get_pci1234.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += get_pci1234.c
# Enable this if you want to check the values of the PCI routing registers.
# Call show_all_routes() anywhere amdfam10.h is included.
#ramstage-y += util.c
@ -30,6 +31,4 @@ s3nv-file := $(obj)/coreboot_s3nv.rom
s3nv-align := $(CONFIG_S3_DATA_SIZE)
s3nv-type := raw
ramstage-$(CONFIG_DIMM_DDR3) += ../amdmct/mct_ddr3/s3utils.c
endif

43
src/northbridge/amd/amdfam10/amdfam10.h
View File

@ -15,8 +15,28 @@
*/
#ifndef AMDFAM10_H
#define AMDFAM10_H
#include <inttypes.h>
#include <arch/io.h>
#include <device/device.h>
#include "early_ht.h"
#include "inline_helper.c"
struct DCTStatStruc;
struct MCTStatStruc;
#define RES_PCI_IO 0x10
#define RES_PORT_IO_8 0x22
#define RES_PORT_IO_32 0x20
#define RES_MEM_IO 0x40
#define NODE_ID 0x60
#define HT_INIT_CONTROL 0x6c
#define HTIC_ColdR_Detect (1<<4)
#define HTIC_BIOSR_Detect (1<<5)
#define HTIC_INIT_Detect (1<<6)
/* Definitions of various FAM10 registers */
/* Function 0 */
#define HT_TRANSACTION_CONTROL 0x68
@ -900,14 +920,8 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#endif
#endif
#include "raminit.h"
#include "../amdmct/wrappers/mcti.h"
#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
#include "../amdmct/mct_ddr3/mct_d.h"
#else
#include "../amdmct/mct/mct_d.h"
#endif
/* Include wrapper for MCT (works for DDR2 or DDR3) */
#include <northbridge/amd/amdmct/wrappers/mcti.h>
struct link_pair_t {
pci_devfn_t udev;
@ -965,10 +979,12 @@ struct sys_info {
struct DCTStatStruc DCTstatA[NODE_NUMS];
} __attribute__((packed));
/*
#ifdef __PRE_RAM__
extern struct sys_info sysinfo_car;
#endif
*/
#ifndef __PRE_RAM__
device_t get_node_pci(u32 nodeid, u32 fn);
#endif
@ -983,14 +999,19 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32
offset_pci_dev, u32 offset_io_base);
void setup_resource_map_x(const u32 *register_values, u32 max);
void setup_resource_map(const u32 *register_values, u32 max);
/* reset_test.c */
u32 cpu_init_detected(u8 nodeid);
u32 bios_reset_detected(void);
u32 cold_reset_detected(void);
u32 other_reset_detected(void);
u32 warm_reset_detect(u8 nodeid);
void distinguish_cpu_resets(u8 nodeid);
u32 get_sblk(void);
u8 get_sbbusn(u8 sblk);
void set_bios_reset(void);
#endif
#include "northbridge/amd/amdht/porting.h"
@ -1005,4 +1026,6 @@ unsigned long northbridge_write_acpi_tables(device_t device,
void northbridge_acpi_write_vars(device_t device);
#endif
void set_sysinfo_in_ram(u32 val);
#endif /* AMDFAM10_H */

4
src/northbridge/amd/amdfam10/amdfam10_util.c
View File

@ -17,8 +17,8 @@
#include <console/console.h>
#include <arch/cpu.h>
#include <northbridge/amd/amdmct/wrappers/mcti.h>
#include <northbridge/amd/amdmct/mct/mct_d.h>
#include <arch/io.h>
#include "raminit.h"
#include <northbridge/amd/amdmct/amddefs.h>
#ifndef __PRE_RAM__

2
src/northbridge/amd/amdfam10/bootblock.c
View File

@ -1,5 +1,3 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include "northbridge/amd/amdfam10/early_ht.c"
static void bootblock_northbridge_init(void) {

65
src/northbridge/amd/amdfam10/debug.c
View File

@ -13,26 +13,25 @@
* GNU General Public License for more details.
*/
/*
* Generic FAM10 debug code, used by mainboard specific romstage.c
*/
#include "pci.c"
#include "debug.h"
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <delay.h>
static inline void print_debug_addr(const char *str, void *val)
void print_debug_addr(const char *str, void *val)
{
#if CONFIG_DEBUG_CAR
printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
#endif
}
static void print_debug_pci_dev(u32 dev)
void print_debug_pci_dev(u32 dev)
{
printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
}
static inline void print_pci_devices(void)
void print_pci_devices(void)
{
pci_devfn_t dev;
for (dev = PCI_DEV(0, 0, 0);
@ -57,7 +56,7 @@ static inline void print_pci_devices(void)
}
}
static inline void print_pci_devices_on_bus(u32 busn)
void print_pci_devices_on_bus(u32 busn)
{
pci_devfn_t dev;
for (dev = PCI_DEV(busn, 0, 0);
@ -82,7 +81,7 @@ static inline void print_pci_devices_on_bus(u32 busn)
}
}
static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
{
int i;
print_debug_pci_dev(dev);
@ -103,12 +102,12 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
printk(BIOS_DEBUG, "\n");
}
static void dump_pci_device(u32 dev)
void dump_pci_device(u32 dev)
{
dump_pci_device_range(dev, 0, 4096);
}
static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
u32 size)
{
int i;
@ -130,13 +129,13 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg)
void dump_pci_device_index_wait(u32 dev, u32 index_reg)
{
dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54);
dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz
}
static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
{
int i;
print_debug_pci_dev(dev);
@ -156,7 +155,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_devices(void)
void dump_pci_devices(void)
{
pci_devfn_t dev;
for (dev = PCI_DEV(0, 0, 0);
@ -181,7 +180,7 @@ static inline void dump_pci_devices(void)
}
}
static inline void dump_pci_devices_on_bus(u32 busn)
void dump_pci_devices_on_bus(u32 busn)
{
pci_devfn_t dev;
for (dev = PCI_DEV(busn, 0, 0);
@ -207,8 +206,7 @@ static inline void dump_pci_devices_on_bus(u32 busn)
}
#if CONFIG_DEBUG_SMBUS
static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
printk(BIOS_DEBUG, "\n");
@ -254,7 +252,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
}
}
}
static void dump_smbus_registers(void)
void dump_smbus_registers(void)
{
u32 device;
printk(BIOS_DEBUG, "\n");
@ -279,7 +278,8 @@ static void dump_smbus_registers(void)
}
}
#endif
static inline void dump_io_resources(u32 port)
void dump_io_resources(u32 port)
{
int i;
@ -299,7 +299,7 @@ static inline void dump_io_resources(u32 port)
}
}
static inline void dump_mem(u32 start, u32 end)
void dump_mem(u32 start, u32 end)
{
u32 i;
printk(BIOS_DEBUG, "dump_mem:");
@ -311,3 +311,26 @@ static inline void dump_mem(u32 start, u32 end)
}
printk(BIOS_DEBUG, "\n");
}
#if IS_ENABLED(CONFIG_DIMM_DDR2)
void print_tx(const char *strval, u32 val)
{
#if CONFIG_DEBUG_RAM_SETUP
printk(BIOS_DEBUG, "%s%08x\n", strval, val);
#endif
}
void print_t(const char *strval)
{
#if CONFIG_DEBUG_RAM_SETUP
printk(BIOS_DEBUG, "%s", strval);
#endif
}
#endif /* CONFIG_DIMM_DDR2 */
void print_tf(const char *func, const char *strval)
{
#if CONFIG_DEBUG_RAM_SETUP
printk(BIOS_DEBUG, "%s: %s", func, strval);
#endif
}

46
src/northbridge/amd/amdfam10/debug.h Normal file
View File

@ -0,0 +1,46 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef AMDFAM10_DEBUG_H
#define AMDFAM10_DEBUG_H
#include <inttypes.h>
#include "pci.h"
void print_debug_addr(const char *str, void *val);
void print_debug_pci_dev(u32 dev);
void print_pci_devices(void);
void print_pci_devices_on_bus(u32 busn);
void dump_pci_device_range(u32 dev, u32 start_reg, u32 size);
void dump_pci_device(u32 dev);
void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
u32 size);
void dump_pci_device_index_wait(u32 dev, u32 index_reg);
void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length);
void dump_pci_devices(void);
void dump_pci_devices_on_bus(u32 busn);
#if CONFIG_DEBUG_SMBUS
void dump_spd_registers(const struct mem_controller *ctrl);
void dump_smbus_registers(void);
#endif
void dump_io_resources(u32 port);
void dump_mem(u32 start, u32 end);
void print_tx(const char *strval, u32 val);
void print_t(const char *strval);
void print_tf(const char *func, const char *strval);
#endif

9
src/northbridge/amd/amdfam10/early_ht.c
View File

@ -13,9 +13,14 @@
* GNU General Public License for more details.
*/
#include "early_ht.h"
#include <inttypes.h>
#include <arch/io.h>
#include <device/pci_def.h>
// For SB HT chain only
// mmconf is not ready yet
static void set_bsp_node_CHtExtNodeCfgEn(void)
void set_bsp_node_CHtExtNodeCfgEn(void)
{
#if CONFIG_EXT_RT_TBL_SUPPORT
u32 dword;
@ -34,7 +39,7 @@ static void set_bsp_node_CHtExtNodeCfgEn(void)
#endif
}
static void enumerate_ht_chain(void)
void enumerate_ht_chain(void)
{
#if CONFIG_HT_CHAIN_UNITID_BASE != 0
/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain),

21
src/northbridge/amd/amdfam10/early_ht.h Normal file
View File

@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef EARLY_HT_H
#define EARLY_HT_H
void set_bsp_node_CHtExtNodeCfgEn(void);
void enumerate_ht_chain(void);
#endif

31
src/northbridge/amd/amdfam10/inline_helper.c Normal file
View File

@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cpu.h>
static inline uint8_t is_fam15h(void)
{
uint8_t fam15h = 0;
uint32_t family;
family = cpuid_eax(0x80000001);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
if (family >= 0x6f)
/* Family 15h or later */
fam15h = 1;
return fam15h;
}

15
src/northbridge/amd/amdfam10/link_control.c
View File

@ -29,21 +29,6 @@
#include "amdfam10.h"
static inline uint8_t is_fam15h(void)
{
uint8_t fam15h = 0;
uint32_t family;
family = cpuid_eax(0x80000001);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
if (family >= 0x6f)
/* Family 15h or later */
fam15h = 1;
return fam15h;
}
static void nb_control_init(struct device *dev)
{
uint8_t enable_c_states;

15
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -81,21 +81,6 @@ device_t get_node_pci(u32 nodeid, u32 fn)
#endif
}
static inline uint8_t is_fam15h(void)
{
uint8_t fam15h = 0;
uint32_t family;
family = cpuid_eax(0x80000001);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
if (family >= 0x6f)
/* Family 15h or later */
fam15h = 1;
return fam15h;
}
static void get_fx_devs(void)
{
int i;

13
src/northbridge/amd/amdfam10/pci.c
View File

@ -13,13 +13,11 @@
* GNU General Public License for more details.
*/
#include "pci.h"
#ifndef AMDFAM10_PCI_C
#define AMDFAM10_PCI_C
/* bit [10,8] are dev func, bit[1,0] are dev index */
static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index)
u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index)
{
u32 dword;
@ -29,7 +27,7 @@ static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index)
}
#ifdef UNUSED_CODE
static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index,
void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index,
u32 data)
{
@ -40,7 +38,7 @@ static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index,
}
#endif
static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg,
u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg,
u32 index)
{
@ -56,7 +54,7 @@ static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg,
}
#ifdef UNUSED_CODE
static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg,
void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg,
u32 index, u32 data)
{
@ -71,4 +69,3 @@ static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg,
}
#endif
#endif

26
src/northbridge/amd/amdfam10/pci.h Normal file
View File

@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef AMDFAM10_PCI_H
#define AMDFAM10_PCI_H
#include <inttypes.h>
#include <arch/io.h>
#include <device/pci_def.h>
u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index);
u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index);
#endif

52
src/northbridge/amd/amdfam10/raminit.h
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -13,31 +13,31 @@
* GNU General Public License for more details.
*/
#ifndef RAMINIT_H
#define RAMINIT_H
#ifndef AMDFAM10_RAMINIT_H
#define AMDFAM10_RAMINIT_H
//DDR2 REG and unbuffered : Socket F 1027 and AM3
/* every channel have 4 DDR2 DIMM for socket F
* 2 for socket M2/M3
* 1 for socket s1g1
*/
#define DIMM_SOCKETS 4
struct mem_controller {
u32 node_id;
pci_devfn_t f0, f1, f2, f3, f4, f5;
/* channel0 is DCT0 --- channelA
* channel1 is DCT1 --- channelB
* can be ganged, a single dual-channel DCT ---> 128 bit
* or unganged a two single-channel DCTs ---> 64bit
* When the DCTs are ganged, the writes to DCT1 set of registers
* (F2x1XX) are ignored and reads return all 0's
* The exception is the DCT phy registers, F2x[1,0]98, F2x[1,0]9C,
* and all the associated indexed registers, are still
* independently accessiable
*/
/* FIXME: I will only support ganged mode for easy support */
u8 spd_switch_addr;
u8 spd_addr[DIMM_SOCKETS*2];
};
#include <device/pci.h>
#include <northbridge/amd/amdmct/amddefs.h>
#include <northbridge/amd/amdmct/wrappers/mcti.h>
struct sys_info;
struct DCTStatStruc;
struct MCTStatStruc;
int mctRead_SPD(u32 smaddr, u32 reg);
void mctSMBhub_Init(u32 node);
void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node);
void raminit_amdmct(struct sys_info *sysinfo);
void amdmct_cbmem_store_info(struct sys_info *sysinfo);
void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr);
uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq);
u8 mctGetProcessorPackageType(void);
void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val);
uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg);
uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index);
void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data);
void fam15h_switch_dct(uint32_t dev, uint8_t dct);
uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg);
void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val);
#endif

160
src/northbridge/amd/amdfam10/raminit_amdmct.c
View File

@ -1,6 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
@ -14,31 +15,26 @@
* GNU General Public License for more details.
*/
#include <inttypes.h>
#include <arch/io.h>
#include <arch/acpi.h>
#include <device/pci.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <northbridge/amd/amdfam10/debug.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */
static void print_tx(const char *strval, u32 val)
{
#if CONFIG_DEBUG_RAM_SETUP
printk(BIOS_DEBUG, "%s%08x\n", strval, val);
#endif
}
/* Global allocation of sysinfo_car */
#include <arch/early_variables.h>
struct sys_info sysinfo_car CAR_GLOBAL;
static void print_t(const char *strval)
{
#if CONFIG_DEBUG_RAM_SETUP
printk(BIOS_DEBUG, "%s", strval);
#endif
}
#endif
struct mem_controller;
extern void activate_spd_rom(const struct mem_controller *ctrl);
extern int spd_read_byte(unsigned device, unsigned address);
static void print_tf(const char *func, const char *strval)
{
#if CONFIG_DEBUG_RAM_SETUP
printk(BIOS_DEBUG, "%s: %s", func, strval);
#endif
}
static inline void fam15h_switch_dct(uint32_t dev, uint8_t dct)
void fam15h_switch_dct(uint32_t dev, uint8_t dct)
{
uint32_t dword;
@ -58,7 +54,7 @@ static inline void fam15h_switch_nb_pstate_config_reg(uint32_t dev, uint8_t nb_p
Set_NB32(dev, 0x10c, dword);
}
static inline uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg)
uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg)
{
if (is_fam15h()) {
/* Obtain address of function 0x1 */
@ -70,7 +66,7 @@ static inline uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg)
}
}
static inline void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val)
void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val)
{
if (is_fam15h()) {
/* Obtain address of function 0x1 */
@ -82,7 +78,7 @@ static inline void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_
}
}
static inline uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg)
uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg)
{
if (is_fam15h()) {
/* Obtain address of function 0x1 */
@ -95,7 +91,7 @@ static inline uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t
}
}
static inline void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val)
void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val)
{
if (is_fam15h()) {
/* Obtain address of function 0x1 */
@ -108,7 +104,7 @@ static inline void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_p
}
}
static inline uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index)
uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index)
{
if (is_fam15h()) {
/* Obtain address of function 0x1 */
@ -120,7 +116,7 @@ static inline uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32
}
}
static inline void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data)
void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data)
{
if (is_fam15h()) {
/* Obtain address of function 0x1 */
@ -144,7 +140,7 @@ static uint16_t voltage_index_to_mv(uint8_t index)
return 1500;
}
static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq)
uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq)
{
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
@ -524,106 +520,6 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8
return freq;
}
#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
#include "amdfam10.h"
#include "../amdmct/wrappers/mcti.h"
#include "../amdmct/amddefs.h"
#include "../amdmct/mct_ddr3/mwlc_d.h"
#include "../amdmct/mct_ddr3/mct_d.h"
#include "../amdmct/mct_ddr3/mct_d_gcc.h"
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#include "../amdmct/mct_ddr3/s3utils.c"
#endif
#include "../amdmct/wrappers/mcti_d.c"
#include "../amdmct/mct_ddr3/mct_d.c"
#include "../amdmct/mct_ddr3/mctmtr_d.c"
#include "../amdmct/mct_ddr3/mctcsi_d.c"
#include "../amdmct/mct_ddr3/mctecc_d.c"
#include "../amdmct/mct_ddr3/mctdqs_d.c"
#include "../amdmct/mct_ddr3/mctsrc.c"
#include "../amdmct/mct_ddr3/mctsdi.c"
#include "../amdmct/mct_ddr3/mctprod.c"
#include "../amdmct/mct_ddr3/mctproc.c"
#include "../amdmct/mct_ddr3/mctprob.c"
#include "../amdmct/mct_ddr3/mcthwl.c"
#include "../amdmct/mct_ddr3/mctwl.c"
#include "../amdmct/mct_ddr3/mport_d.c"
#include "../amdmct/mct_ddr3/mutilc_d.c"
#include "../amdmct/mct_ddr3/modtrdim.c"
#include "../amdmct/mct_ddr3/mhwlc_d.c"
#include "../amdmct/mct_ddr3/mctrci.c"
#include "../amdmct/mct_ddr3/mctsrc1p.c"
#include "../amdmct/mct_ddr3/mcttmrl.c"
#include "../amdmct/mct_ddr3/mcthdi.c"
#include "../amdmct/mct_ddr3/mctndi_d.c"
#include "../amdmct/mct_ddr3/mctchi_d.c"
#include "../amdmct/mct_ddr3/modtrd.c"
#if CONFIG_CPU_SOCKET_TYPE == 0x10
//TODO: S1G1?
#elif CONFIG_CPU_SOCKET_TYPE == 0x11
//AM3
#include "../amdmct/mct_ddr3/mctardk5.c"
#elif CONFIG_CPU_SOCKET_TYPE == 0x12
//F (1207), Fr2, G (1207)
#include "../amdmct/mct_ddr3/mctardk6.c"
#elif CONFIG_CPU_SOCKET_TYPE == 0x13
//ASB2
#include "../amdmct/mct_ddr3/mctardk5.c"
//C32
#elif CONFIG_CPU_SOCKET_TYPE == 0x14
#include "../amdmct/mct_ddr3/mctardk5.c"
//G34
#elif CONFIG_CPU_SOCKET_TYPE == 0x15
#include "../amdmct/mct_ddr3/mctardk5.c"
//FM2
#elif CONFIG_CPU_SOCKET_TYPE == 0x16
#include "../amdmct/mct_ddr3/mctardk5.c"
#endif
#else /* DDR2 */
#include "amdfam10.h"
#include "../amdmct/wrappers/mcti.h"
#include "../amdmct/amddefs.h"
#include "../amdmct/mct/mct_d.h"
#include "../amdmct/mct/mct_d_gcc.h"
#include "../amdmct/wrappers/mcti_d.c"
#include "../amdmct/mct/mct_d.c"
#include "../amdmct/mct/mctmtr_d.c"
#include "../amdmct/mct/mctcsi_d.c"
#include "../amdmct/mct/mctecc_d.c"
#include "../amdmct/mct/mctpro_d.c"
#include "../amdmct/mct/mctdqs_d.c"
#include "../amdmct/mct/mctsrc.c"
#include "../amdmct/mct/mctsrc1p.c"
#include "../amdmct/mct/mcttmrl.c"
#include "../amdmct/mct/mcthdi.c"
#include "../amdmct/mct/mctndi_d.c"
#include "../amdmct/mct/mctchi_d.c"
#if CONFIG_CPU_SOCKET_TYPE == 0x10
//L1
#include "../amdmct/mct/mctardk3.c"
#elif CONFIG_CPU_SOCKET_TYPE == 0x11
//AM2
#include "../amdmct/mct/mctardk4.c"
//#elif SYSTEM_TYPE == MOBILE
//s1g1
//#include "../amdmct/mct/mctardk5.c"
#endif
#endif /* DDR2 */
#include <arch/early_variables.h>
struct sys_info sysinfo_car CAR_GLOBAL;
int mctRead_SPD(u32 smaddr, u32 reg)
{
return spd_read_byte(smaddr, reg);
@ -652,14 +548,14 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
}
#if IS_ENABLED(CONFIG_SET_FIDVID)
static u8 mctGetProcessorPackageType(void) {
u8 mctGetProcessorPackageType(void) {
/* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */
u32 BrandId = cpuid_ebx(0x80000001);
return (u8)((BrandId >> 28) & 0x0F);
}
#endif
static void raminit_amdmct(struct sys_info *sysinfo)
void raminit_amdmct(struct sys_info *sysinfo)
{
struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
@ -671,7 +567,7 @@ static void raminit_amdmct(struct sys_info *sysinfo)
printk(BIOS_DEBUG, "raminit_amdmct end:\n");
}
static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
void amdmct_cbmem_store_info(struct sys_info *sysinfo)
{
if (!sysinfo)
return;

14
src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
View File

@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <delay.h>
static void set_htic_bit(u8 i, u32 val, u8 bit)
@ -45,12 +47,7 @@ static void wait_till_sysinfo_in_ram(void)
}
#endif
static void set_sysinfo_in_ram(u32 val)
{
set_htic_bit(0, val, 9);
}
static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr)
void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr)
{
int i;
int j;
@ -76,3 +73,8 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const
}
}
}
void set_sysinfo_in_ram(u32 val)
{
set_htic_bit(0, val, 9);
}

14
src/northbridge/amd/amdfam10/reset_test.c
View File

@ -15,13 +15,8 @@
#include <stdint.h>
#include <cpu/x86/lapic.h>
#include "amdfam10.h"
#define NODE_ID 0x60
#define HT_INIT_CONTROL 0x6c
#define HTIC_ColdR_Detect (1<<4)
#define HTIC_BIOSR_Detect (1<<5)
#define HTIC_INIT_Detect (1<<6)
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
/* mmconf is not ready */
/* io_ext is not ready */
@ -60,7 +55,7 @@ u32 other_reset_detected(void) // other warm reset not started by BIOS
return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect);
}
static void distinguish_cpu_resets(u8 nodeid)
void distinguish_cpu_resets(u8 nodeid)
{
u32 htic;
pci_devfn_t device;
@ -70,7 +65,7 @@ static void distinguish_cpu_resets(u8 nodeid)
pci_io_write_config32(device, HT_INIT_CONTROL, htic);
}
static u32 warm_reset_detect(u8 nodeid)
u32 warm_reset_detect(u8 nodeid)
{
u32 htic;
pci_devfn_t device;
@ -79,7 +74,6 @@ static u32 warm_reset_detect(u8 nodeid)
return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
}
void set_bios_reset(void);
void set_bios_reset(void)
{

11
src/northbridge/amd/amdfam10/setup_resource_map.c
View File

@ -14,10 +14,14 @@
* GNU General Public License for more details.
*/
#include <inttypes.h>
#include <console/console.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#define RES_DEBUG 0
static void setup_resource_map(const u32 *register_values, u32 max)
void setup_resource_map(const u32 *register_values, u32 max)
{
u32 i;
@ -53,11 +57,6 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p
}
}
#define RES_PCI_IO 0x10
#define RES_PORT_IO_8 0x22
#define RES_PORT_IO_32 0x20
#define RES_MEM_IO 0x40
void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base)
{
u32 i;

5
src/northbridge/amd/amdht/Makefile.inc Normal file
View File

@ -0,0 +1,5 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y)
romstage-y += h3finit.c ht_wrapper.c comlib.c AsPsNb.c h3ncmn.c
endif

7
src/northbridge/amd/amdht/comlib.c
View File

@ -17,6 +17,13 @@
#define FILECODE 0xCCCC
#include "comlib.h"
#include <device/pci.h>
#include <console/console.h>
#include <cpu/amd/msr.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
/*
*---------------------------------------------------------------------------
* EXPORTED FUNCTIONS

11
src/northbridge/amd/amdht/comlib.h
View File

@ -16,16 +16,13 @@
#ifndef COMLIB_H
#define COMLIB_H
#ifndef FILECODE
#error "FILECODE was not defined, should be #define'd to 0xFxxx"
#endif
#undef FILECODE
#define FILECODE 0xF001
#include <inttypes.h>
#include <stdlib.h>
#include "porting.h"
/* include coreboot pci functions */
#include <device/pci_def.h>
#include <device/pci_ids.h>
#ifdef AMD_DEBUG
#define ASSERT(x) ((x) ? 0 : ErrorStop(((uint32)FILECODE)*0x10000 + ((__LINE__)%10) + (((__LINE__/10)%10)*0x10) + (((__LINE__/100)%10)*0x100) +(((__LINE__/1000)%10)*0x1000)))
#else

2
src/northbridge/amd/amdht/h3ffeat.h
View File

@ -18,6 +18,8 @@
#ifndef H3FFEAT_H
#define H3FFEAT_H
#include "h3finit.h"
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*

20
src/northbridge/amd/amdht/h3finit.c
View File

@ -21,19 +21,20 @@
*----------------------------------------------------------------------------
*/
#undef FILECODE
#define FILECODE 0xF001
#include "comlib.h"
#include "h3finit.h"
#include "h3ffeat.h"
#include "h3ncmn.h"
#include "h3gtopo.h"
#include "AsPsNb.h"
/* this is pre-ram so include the required C files here */
#include "comlib.c"
#include "AsPsNb.c"
#include "h3ncmn.c"
#include <device/pci.h>
#include <console/console.h>
#include <cpu/amd/msr.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
@ -41,9 +42,6 @@
*----------------------------------------------------------------------------
*/
#undef FILECODE
#define FILECODE 0xF001
/* APIC defines from amdgesa.inc, which can't be included in to c code. */
#define APIC_Base_BSP 8
#define APIC_Base 0x1b

2
src/northbridge/amd/amdht/h3finit.h
View File

@ -17,6 +17,8 @@
#ifndef H3FINIT_H
#define H3FINIT_H
#include "comlib.h"
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*

27
src/northbridge/amd/amdht/h3ncmn.c
View File

@ -23,11 +23,19 @@
#undef FILECODE
#define FILECODE 0xF002
#include "h3ncmn.h"
#include "h3finit.h"
#include "h3ffeat.h"
#include "h3ncmn.h"
#include "AsPsNb.h"
#include <device/pci.h>
#include <console/console.h>
#include <cpu/amd/msr.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
@ -89,22 +97,7 @@
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
static inline uint8_t is_fam15h(void)
{
uint8_t fam15h = 0;
uint32_t family;
family = cpuid_eax(0x80000001);
family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
if (family >= 0x6f)
/* Family 15h or later */
fam15h = 1;
return fam15h;
}
static inline uint8_t is_gt_rev_d(void)
inline uint8_t is_gt_rev_d(void)
{
uint8_t fam15h = 0;
uint8_t rev_gte_d = 0;

30
src/northbridge/amd/amdht/h3ncmn.h
View File

@ -17,17 +17,13 @@
#ifndef H3NCMN_H
#define H3NCMN_H
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
#include <inttypes.h>
#include <device/pci.h>
#include <console/console.h>
#include <cpu/amd/msr.h>
#include "comlib.h"
#include "h3finit.h"
#include "h3ffeat.h"
/* Use a macro to convert a node number to a PCI device. If some future port of
* this code needs to, this can easily be replaced by a function call:
@ -65,12 +61,6 @@
((u16)fc & HT_FREQUENCY_LIMIT_HT1_ONLY)
#endif
/*----------------------------------------------------------------------------
* TYPEDEFS, STRUCTURES, ENUMS
*
*----------------------------------------------------------------------------
*/
struct cNorthBridge
{
/* Public data, clients of northbridge can access */
@ -119,11 +109,7 @@ struct cNorthBridge
u32 compatibleKey;
} ;
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
void newNorthBridge(u8 node, cNorthBridge *nb);
uint8_t is_gt_rev_d(void);
#endif /* H3NCMN_H */

44
src/northbridge/amd/amdht/ht_wrapper.c
View File

@ -16,8 +16,6 @@
#include <cpu/x86/msr.h>
#include <console/console.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "ht_wrapper.h"
/*----------------------------------------------------------------------------
@ -51,37 +49,12 @@
#include "h3gtopo.h"
#include "h3finit.h"
/* include the main HT source file */
#include "h3finit.c"
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/* FIXME: Find a better place for these pre-ram functions. */
#define NODE_HT(x) NODE_PCI(x,0)
#define NODE_MP(x) NODE_PCI(x,1)
#define NODE_MC(x) NODE_PCI(x,3)
#define NODE_LC(x) NODE_PCI(x,4)
static u32 get_nodes(void)
{
pci_devfn_t dev;
u32 nodes;
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0);
nodes = ((pci_read_config32(dev, 0x60)>>4) & 7);
#if CONFIG_MAX_PHYSICAL_CPUS > 8
nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3);
#endif
nodes++;
return nodes;
}
static const char * event_class_string_decodes[] = {
[HT_EVENT_CLASS_CRITICAL] = "CRITICAL",
[HT_EVENT_CLASS_ERROR] = "ERROR",
@ -255,7 +228,7 @@ static BOOL AMD_CB_IgnoreLink (u8 node, u8 link)
* AMD HT init coreboot wrapper
*
*/
static void amd_ht_init(struct sys_info *sysinfo)
void amd_ht_init(struct sys_info *sysinfo)
{
if (!sysinfo) {
@ -390,3 +363,18 @@ void amd_ht_fixup(struct sys_info *sysinfo) {
}
}
}
u32 get_nodes(void)
{
pci_devfn_t dev;
u32 nodes;
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0);
nodes = ((pci_read_config32(dev, 0x60)>>4) & 7);
#if CONFIG_MAX_PHYSICAL_CPUS > 8
nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3);
#endif
nodes++;
return nodes;
}

7
src/northbridge/amd/amdht/ht_wrapper.h
View File

@ -16,6 +16,13 @@
#ifndef AMD_HT_WRAPPER_H
#define AMD_HT_WRAPPER_H
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <inttypes.h>
#include "h3finit.h"
void amd_ht_fixup(struct sys_info *sysinfo);
u32 get_nodes(void);
void amd_ht_init(struct sys_info *sysinfo);
#endif

28
src/northbridge/amd/amdmct/amddefs.h
View File

@ -13,6 +13,8 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef AMDDEFS_H
#define AMDDEFS_H
/* FIXME: this file should be moved to include/cpu/amd/amddefs.h */
@ -163,3 +165,29 @@
#define AMD_PKGTYPE_ASB2 4
#define AMD_PKGTYPE_C32 5
#define AMD_PKGTYPE_FM2 6
//DDR2 REG and unbuffered : Socket F 1027 and AM3
/* every channel have 4 DDR2 DIMM for socket F
* 2 for socket M2/M3
* 1 for socket s1g1
*/
#define DIMM_SOCKETS 4
struct mem_controller {
u32 node_id;
pci_devfn_t f0, f1, f2, f3, f4, f5;
/* channel0 is DCT0 --- channelA
* channel1 is DCT1 --- channelB
* can be ganged, a single dual-channel DCT ---> 128 bit
* or unganged a two single-channel DCTs ---> 64bit
* When the DCTs are ganged, the writes to DCT1 set of registers
* (F2x1XX) are ignored and reads return all 0's
* The exception is the DCT phy registers, F2x[1,0]98, F2x[1,0]9C,
* and all the associated indexed registers, are still
* independently accessiable
*/
/* FIXME: I will only support ganged mode for easy support */
u8 spd_switch_addr;
u8 spd_addr[DIMM_SOCKETS*2];
};
#endif

16
src/northbridge/amd/amdmct/mct/Makefile.inc Normal file
View File

@ -0,0 +1,16 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y)
# DDR2
romstage-y += mct_d.c mct_d_gcc.c mctcsi_d.c mctmtr_d.c mctecc_d.c
romstage-y += mctpro_d.c mctdqs_d.c mctsrc.c mctsrc1p.c mcttmrl.c
romstage-y += mcthdi.c mctndi_d.c mctchi_d.c
ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x10)
romstage-y += mctardk3.c
endif
ifeq ($(CONFIG_CPU_SOCKET_TYPE), 0x11)
romstage-y += mctardk4.c
endif
endif

29
src/northbridge/amd/amdmct/mct/mct_d.c
View File

@ -33,6 +33,8 @@
* supported.
*/
#include "mct_d.h"
static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA);
static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
@ -41,15 +43,8 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA);
static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA);
static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA);
static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat);
static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat);
static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA);
static u8 NodePresent_D(u8 Node);
static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA);
static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
@ -66,6 +61,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct);
static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct);
static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct);
static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct);
static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
@ -81,8 +78,6 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat);
static void mct_DramInit(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct);
static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct);
static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat);
static void Get_Trdrd(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct);
@ -175,7 +170,9 @@ static const u8 Table_Comp_Rise_Slew_15x[] = {7, 7, 3, 2, 0xFF};
static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF};
static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF};
static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2};
void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA)
{
/*
@ -661,7 +658,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
}
static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA)
{
@ -693,7 +690,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
}
static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat)
{
u32 val;
@ -716,7 +713,7 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
}
static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat,
void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA)
{
/* Ensures that memory clear has completed on all node.*/
@ -768,7 +765,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
}
static u8 NodePresent_D(u8 Node)
u8 NodePresent_D(u8 Node)
{
/*
* Determine if a single Hammer Node exists within the network.
@ -3655,7 +3652,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
}
static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 *dqs_pos)
{
// FIXME: Skip for Ax
@ -3907,7 +3904,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
}
static void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat,
void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat)
{
u32 dev = pDCTstat->dev_dct;

47
src/northbridge/amd/amdmct/mct/mct_d.h
View File

@ -20,7 +20,18 @@
#ifndef MCT_D_H
#define MCT_D_H
#define DQS_TRAIN_DEBUG 0
#include <inttypes.h>
#include "mct_d_gcc.h"
#include <console/console.h>
#include <northbridge/amd/amdfam10/debug.h>
#include <northbridge/amd/amdfam10/raminit.h>
extern const u8 Table_DQSRcvEn_Offset[];
extern const u32 TestPattern0_D[];
extern const u32 TestPattern1_D[];
extern const u32 TestPattern2_D[];
/*===========================================================================
CPU - K8/FAM10
@ -689,6 +700,8 @@ struct DCTStatStruc { /* A per Node structure*/
#define NV_MAX_DIMMS_PER_CH 64 /* Maximum number of DIMMs per channel */
#include <northbridge/amd/amdfam10/amdfam10.h>
/*===============================================================================
CBMEM storage
===============================================================================*/
@ -735,9 +748,6 @@ void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs
void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC);
u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val);
void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct);
void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node);
void mctSMBhub_Init(u32 node);
int mctRead_SPD(u32 smaddr, u32 reg);
void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
@ -753,4 +763,35 @@ u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC
u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid);
void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr);
void EarlySampleSupport_D(void);
void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 *dqs_pos);
void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat);
void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA);
void beforeInterleaveChannels_D(struct DCTStatStruc *pDCTstatA, u8 *enabled);
u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 DQSDelay,
u8 ChipSel, u8 *result);
void proc_IOCLFLUSH_D(u32 addr_hi);
void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat,
u32 TestAddr, u8 pattern);
u8 NodePresent_D(u8 Node);
void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat);
void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA);
void print_debug_dqs(const char *str, u32 val, u8 level);
void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level);
u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat);
void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index);
void SetTargetWTIO_D(u32 TestAddr);
void ResetTargetWTIO_D(void);
u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 Channel,
u8 receiver, u8 *valid);
#endif

351
src/northbridge/amd/amdmct/mct/mct_d_gcc.c Normal file
View File

@ -0,0 +1,351 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "mct_d_gcc.h"
inline void _WRMSR(u32 addr, u32 lo, u32 hi)
{
__asm__ volatile (
"wrmsr"
:
:"c"(addr),"a"(lo), "d" (hi)
);
}
inline void _RDMSR(u32 addr, u32 *lo, u32 *hi)
{
__asm__ volatile (
"rdmsr"
:"=a"(*lo), "=d" (*hi)
:"c"(addr)
);
}
inline void _RDTSC(u32 *lo, u32 *hi)
{
__asm__ volatile (
"rdtsc"
: "=a" (*lo), "=d"(*hi)
);
}
inline void _cpu_id(u32 addr, u32 *val)
{
__asm__ volatile(
"cpuid"
: "=a" (val[0]),
"=b" (val[1]),
"=c" (val[2]),
"=d" (val[3])
: "0" (addr));
}
u32 bsr(u32 x)
{
u8 i;
u32 ret = 0;
for (i = 31; i > 0; i--) {
if (x & (1<<i)) {
ret = i;
break;
}
}
return ret;
}
u32 bsf(u32 x)
{
u8 i;
u32 ret = 32;
for (i = 0; i < 32; i++) {
if (x & (1<<i)) {
ret = i;
break;
}
}
return ret;
}
#define _MFENCE asm volatile ("mfence")
#define _SFENCE asm volatile ("sfence")
/* prevent speculative execution of following instructions */
#define _EXECFENCE asm volatile ("outb %al, $0xed")
#include <cpu/x86/cr.h>
void proc_CLFLUSH(u32 addr_hi)
{
SetUpperFSbase(addr_hi);
__asm__ volatile (
/* clflush fs:[eax] */
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"clflush %%fs:(%0)\n\t"
"mfence\n\t"
::"a" (addr_hi<<8)
);
}
void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num)
{
__asm__ volatile (
/*prevent speculative execution of following instructions*/
/* FIXME: needed ? */
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"1:\n\t"
"movdqa (%3), %%xmm0\n\t"
"movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */
"addl %1, %0\n\t"
"addl %1, %3\n\t"
"loop 1b\n\t"
"mfence\n\t"
:: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a)
);
}
u32 read32_fs(u32 addr_lo)
{
u32 value;
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"movl %%fs:(%1), %0\n\t"
:"=b"(value): "a" (addr_lo)
);
return value;
}
#ifdef UNUSED_CODE
static u8 read8_fs(u32 addr_lo)
{
u8 byte;
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"movb %%fs:(%1), %b0\n\t"
"mfence\n\t"
:"=b"(byte): "a" (addr_lo)
);
return byte;
}
#endif
void FlushDQSTestPattern_L9(u32 addr_lo)
{
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"clflush %%fs:-128(%%ecx)\n\t"
"clflush %%fs:-64(%%ecx)\n\t"
"clflush %%fs:(%%ecx)\n\t"
"clflush %%fs:64(%%ecx)\n\t"
"clflush %%fs:-128(%%eax)\n\t"
"clflush %%fs:-64(%%eax)\n\t"
"clflush %%fs:(%%eax)\n\t"
"clflush %%fs:64(%%eax)\n\t"
"clflush %%fs:-128(%%ebx)\n\t"
:: "b" (addr_lo+128+8*64), "c"(addr_lo+128),
"a"(addr_lo+128+4*64)
);
}
__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo)
{
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"clflush %%fs:-128(%%eax)\n\t"
"clflush %%fs:-64(%%eax)\n\t"
"clflush %%fs:(%%eax)\n\t"
"clflush %%fs:64(%%eax)\n\t"
"clflush %%fs:-128(%%edi)\n\t"
"clflush %%fs:-64(%%edi)\n\t"
"clflush %%fs:(%%edi)\n\t"
"clflush %%fs:64(%%edi)\n\t"
"clflush %%fs:-128(%%ebx)\n\t"
"clflush %%fs:-64(%%ebx)\n\t"
"clflush %%fs:(%%ebx)\n\t"
"clflush %%fs:64(%%ebx)\n\t"
"clflush %%fs:-128(%%ecx)\n\t"
"clflush %%fs:-64(%%ecx)\n\t"
"clflush %%fs:(%%ecx)\n\t"
"clflush %%fs:64(%%ecx)\n\t"
"clflush %%fs:-128(%%edx)\n\t"
"clflush %%fs:-64(%%edx)\n\t"
:: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64),
"d" (addr_lo +128+16*64), "a"(addr_lo+128),
"D"(addr_lo+128+4*64)
);
}
void ReadL18TestPattern(u32 addr_lo)
{
// set fs and use fs prefix to access the mem
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
"movl %%fs:-64(%%esi), %%eax\n\t" //+1
"movl %%fs:(%%esi), %%eax\n\t" //+2
"movl %%fs:64(%%esi), %%eax\n\t" //+3
"movl %%fs:-128(%%edi), %%eax\n\t" //+4
"movl %%fs:-64(%%edi), %%eax\n\t" //+5
"movl %%fs:(%%edi), %%eax\n\t" //+6
"movl %%fs:64(%%edi), %%eax\n\t" //+7
"movl %%fs:-128(%%ebx), %%eax\n\t" //+8
"movl %%fs:-64(%%ebx), %%eax\n\t" //+9
"movl %%fs:(%%ebx), %%eax\n\t" //+10
"movl %%fs:64(%%ebx), %%eax\n\t" //+11
"movl %%fs:-128(%%ecx), %%eax\n\t" //+12
"movl %%fs:-64(%%ecx), %%eax\n\t" //+13
"movl %%fs:(%%ecx), %%eax\n\t" //+14
"movl %%fs:64(%%ecx), %%eax\n\t" //+15
"movl %%fs:-128(%%edx), %%eax\n\t" //+16
"movl %%fs:-64(%%edx), %%eax\n\t" //+17
"mfence\n\t"
:: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64),
"d" (addr_lo +128+16*64), "S"(addr_lo+128),
"D"(addr_lo+128+4*64)
);
}
void ReadL9TestPattern(u32 addr_lo)
{
// set fs and use fs prefix to access the mem
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line
"movl %%fs:-64(%%ecx), %%eax\n\t" //+1
"movl %%fs:(%%ecx), %%eax\n\t" //+2
"movl %%fs:64(%%ecx), %%eax\n\t" //+3
"movl %%fs:-128(%%edx), %%eax\n\t" //+4
"movl %%fs:-64(%%edx), %%eax\n\t" //+5
"movl %%fs:(%%edx), %%eax\n\t" //+6
"movl %%fs:64(%%edx), %%eax\n\t" //+7
"movl %%fs:-128(%%ebx), %%eax\n\t" //+8
"mfence\n\t"
:: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128),
"d"(addr_lo+128+4*64)
);
}
void ReadMaxRdLat1CLTestPattern_D(u32 addr)
{
SetUpperFSbase(addr);
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
"movl %%fs:-64(%%esi), %%eax\n\t" //+1
"movl %%fs:(%%esi), %%eax\n\t" //+2
"mfence\n\t"
:: "a"(0), "S"((addr<<8)+128)
);
}
void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr)
{
SetUpperFSbase(addr);
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"1:\n\t"
"movdqa (%3), %%xmm0\n\t"
"movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */
"addl %1, %0\n\t"
"addl %1, %3\n\t"
"loop 1b\n\t"
"mfence\n\t"
:: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf)
);
}
void FlushMaxRdLatTestPattern_D(u32 addr)
{
/* Flush a pattern of 72 bit times (per DQ) from cache.
* This procedure is used to ensure cache miss on the next read training.
*/
SetUpperFSbase(addr);
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"clflush %%fs:-128(%%esi)\n\t" //TestAddr cache line
"clflush %%fs:-64(%%esi)\n\t" //+1
"clflush %%fs:(%%esi)\n\t" //+2
"mfence\n\t"
:: "S"((addr<<8)+128)
);
}
u32 stream_to_int(u8 const *p)
{
int i;
u32 val;
u32 valx;
val = 0;
for (i = 3; i >= 0; i--) {
val <<= 8;
valx = *(p+i);
val |= valx;
}
return val;
}
u8 oemNodePresent_D(u8 Node, u8 *ret)
{
*ret = 0;
return 0;
}

368
src/northbridge/amd/amdmct/mct/mct_d_gcc.h
View File

@ -13,362 +13,36 @@
* GNU General Public License for more details.
*/
#ifndef MCT_D_GCC_H
#define MCT_D_GCC_H
static inline void _WRMSR(u32 addr, u32 lo, u32 hi)
{
__asm__ volatile (
"wrmsr"
:
:"c"(addr),"a"(lo), "d" (hi)
);
}
#include <inttypes.h>
static inline void _RDMSR(u32 addr, u32 *lo, u32 *hi)
{
__asm__ volatile (
"rdmsr"
:"=a"(*lo), "=d" (*hi)
:"c"(addr)
);
}
static inline void _RDTSC(u32 *lo, u32 *hi)
{
__asm__ volatile (
"rdtsc"
: "=a" (*lo), "=d"(*hi)
);
}
static inline void _cpu_id(u32 addr, u32 *val)
{
__asm__ volatile(
"cpuid"
: "=a" (val[0]),
"=b" (val[1]),
"=c" (val[2]),
"=d" (val[3])
: "0" (addr));
}
static u32 bsr(u32 x)
{
u8 i;
u32 ret = 0;
for (i = 31; i > 0; i--) {
if (x & (1<<i)) {
ret = i;
break;
}
}
return ret;
}
static u32 bsf(u32 x)
{
u8 i;
u32 ret = 32;
for (i = 0; i < 32; i++) {
if (x & (1<<i)) {
ret = i;
break;
}
}
return ret;
}
void _WRMSR(u32 addr, u32 lo, u32 hi);
void _RDMSR(u32 addr, u32 *lo, u32 *hi);
void _RDTSC(u32 *lo, u32 *hi);
void _cpu_id(u32 addr, u32 *val);
u32 bsr(u32 x);
u32 bsf(u32 x);
#define _MFENCE asm volatile ("mfence")
#define _SFENCE asm volatile ("sfence")
/* prevent speculative execution of following instructions */
#define _EXECFENCE asm volatile ("outb %al, $0xed")
#include <cpu/x86/cr.h>
u32 SetUpperFSbase(u32 addr_hi);
void proc_CLFLUSH(u32 addr_hi);
void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num);
u32 read32_fs(u32 addr_lo);
void FlushDQSTestPattern_L9(u32 addr_lo);
__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo);
void ReadL18TestPattern(u32 addr_lo);
void ReadL9TestPattern(u32 addr_lo);
void ReadMaxRdLat1CLTestPattern_D(u32 addr);
void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr);
void FlushMaxRdLatTestPattern_D(u32 addr);
u32 stream_to_int(u8 const *p);
u8 oemNodePresent_D(u8 Node, u8 *ret);
static void proc_CLFLUSH(u32 addr_hi)
{
SetUpperFSbase(addr_hi);
__asm__ volatile (
/* clflush fs:[eax] */
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"clflush %%fs:(%0)\n\t"
"mfence\n\t"
::"a" (addr_hi<<8)
);
}
static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num)
{
__asm__ volatile (
/*prevent speculative execution of following instructions*/
/* FIXME: needed ? */
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"1:\n\t"
"movdqa (%3), %%xmm0\n\t"
"movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */
"addl %1, %0\n\t"
"addl %1, %3\n\t"
"loop 1b\n\t"
"mfence\n\t"
:: "a" (addr_lo), "d" (16), "c" (line_num * 4), "b"(buf_a)
);
}
static u32 read32_fs(u32 addr_lo)
{
u32 value;
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"movl %%fs:(%1), %0\n\t"
:"=b"(value): "a" (addr_lo)
);
return value;
}
#ifdef UNUSED_CODE
static u8 read8_fs(u32 addr_lo)
{
u8 byte;
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"movb %%fs:(%1), %b0\n\t"
"mfence\n\t"
:"=b"(byte): "a" (addr_lo)
);
return byte;
}
#endif
static void FlushDQSTestPattern_L9(u32 addr_lo)
{
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"clflush %%fs:-128(%%ecx)\n\t"
"clflush %%fs:-64(%%ecx)\n\t"
"clflush %%fs:(%%ecx)\n\t"
"clflush %%fs:64(%%ecx)\n\t"
"clflush %%fs:-128(%%eax)\n\t"
"clflush %%fs:-64(%%eax)\n\t"
"clflush %%fs:(%%eax)\n\t"
"clflush %%fs:64(%%eax)\n\t"
"clflush %%fs:-128(%%ebx)\n\t"
:: "b" (addr_lo+128+8*64), "c"(addr_lo+128),
"a"(addr_lo+128+4*64)
);
}
static __attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo)
{
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"clflush %%fs:-128(%%eax)\n\t"
"clflush %%fs:-64(%%eax)\n\t"
"clflush %%fs:(%%eax)\n\t"
"clflush %%fs:64(%%eax)\n\t"
"clflush %%fs:-128(%%edi)\n\t"
"clflush %%fs:-64(%%edi)\n\t"
"clflush %%fs:(%%edi)\n\t"
"clflush %%fs:64(%%edi)\n\t"
"clflush %%fs:-128(%%ebx)\n\t"
"clflush %%fs:-64(%%ebx)\n\t"
"clflush %%fs:(%%ebx)\n\t"
"clflush %%fs:64(%%ebx)\n\t"
"clflush %%fs:-128(%%ecx)\n\t"
"clflush %%fs:-64(%%ecx)\n\t"
"clflush %%fs:(%%ecx)\n\t"
"clflush %%fs:64(%%ecx)\n\t"
"clflush %%fs:-128(%%edx)\n\t"
"clflush %%fs:-64(%%edx)\n\t"
:: "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64),
"d" (addr_lo +128+16*64), "a"(addr_lo+128),
"D"(addr_lo+128+4*64)
);
}
static void ReadL18TestPattern(u32 addr_lo)
{
// set fs and use fs prefix to access the mem
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
"movl %%fs:-64(%%esi), %%eax\n\t" //+1
"movl %%fs:(%%esi), %%eax\n\t" //+2
"movl %%fs:64(%%esi), %%eax\n\t" //+3
"movl %%fs:-128(%%edi), %%eax\n\t" //+4
"movl %%fs:-64(%%edi), %%eax\n\t" //+5
"movl %%fs:(%%edi), %%eax\n\t" //+6
"movl %%fs:64(%%edi), %%eax\n\t" //+7
"movl %%fs:-128(%%ebx), %%eax\n\t" //+8
"movl %%fs:-64(%%ebx), %%eax\n\t" //+9
"movl %%fs:(%%ebx), %%eax\n\t" //+10
"movl %%fs:64(%%ebx), %%eax\n\t" //+11
"movl %%fs:-128(%%ecx), %%eax\n\t" //+12
"movl %%fs:-64(%%ecx), %%eax\n\t" //+13
"movl %%fs:(%%ecx), %%eax\n\t" //+14
"movl %%fs:64(%%ecx), %%eax\n\t" //+15
"movl %%fs:-128(%%edx), %%eax\n\t" //+16
"movl %%fs:-64(%%edx), %%eax\n\t" //+17
"mfence\n\t"
:: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64),
"d" (addr_lo +128+16*64), "S"(addr_lo+128),
"D"(addr_lo+128+4*64)
);
}
static void ReadL9TestPattern(u32 addr_lo)
{
// set fs and use fs prefix to access the mem
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"movl %%fs:-128(%%ecx), %%eax\n\t" //TestAddr cache line
"movl %%fs:-64(%%ecx), %%eax\n\t" //+1
"movl %%fs:(%%ecx), %%eax\n\t" //+2
"movl %%fs:64(%%ecx), %%eax\n\t" //+3
"movl %%fs:-128(%%edx), %%eax\n\t" //+4
"movl %%fs:-64(%%edx), %%eax\n\t" //+5
"movl %%fs:(%%edx), %%eax\n\t" //+6
"movl %%fs:64(%%edx), %%eax\n\t" //+7
"movl %%fs:-128(%%ebx), %%eax\n\t" //+8
"mfence\n\t"
:: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128),
"d"(addr_lo+128+4*64)
);
}
static void ReadMaxRdLat1CLTestPattern_D(u32 addr)
{
SetUpperFSbase(addr);
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
"movl %%fs:-64(%%esi), %%eax\n\t" //+1
"movl %%fs:(%%esi), %%eax\n\t" //+2
"mfence\n\t"
:: "a"(0), "S"((addr<<8)+128)
);
}
static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr)
{
SetUpperFSbase(addr);
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"1:\n\t"
"movdqa (%3), %%xmm0\n\t"
"movntdq %%xmm0, %%fs:(%0)\n\t" /* xmm0 is 128 bit */
"addl %1, %0\n\t"
"addl %1, %3\n\t"
"loop 1b\n\t"
"mfence\n\t"
:: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf)
);
}
static void FlushMaxRdLatTestPattern_D(u32 addr)
{
/* Flush a pattern of 72 bit times (per DQ) from cache.
* This procedure is used to ensure cache miss on the next read training.
*/
SetUpperFSbase(addr);
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
"clflush %%fs:-128(%%esi)\n\t" //TestAddr cache line
"clflush %%fs:-64(%%esi)\n\t" //+1
"clflush %%fs:(%%esi)\n\t" //+2
"mfence\n\t"
:: "S"((addr<<8)+128)
);
}
static u32 stream_to_int(u8 const *p)
{
int i;
u32 val;
u32 valx;
val = 0;
for (i = 3; i >= 0; i--) {
val <<= 8;
valx = *(p+i);
val |= valx;
}
return val;
}
#ifdef UNUSED_CODE
static void oemSet_NB32(u32 addr, u32 val, u8 *valid)
{
}
static u32 oemGet_NB32(u32 addr, u8 *valid)
{
*valid = 0;
return 0xffffffff;
}
#endif
static u8 oemNodePresent_D(u8 Node, u8 *ret)
{
*ret = 0;
return 0;
}

2
src/northbridge/amd/amdmct/mct/mctardk3.c
View File

@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#include <inttypes.h>
#include "mct_d.h"
static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL);

2
src/northbridge/amd/amdmct/mct/mctardk4.c
View File

@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#include <inttypes.h>
#include "mct_d.h"
static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,

2
src/northbridge/amd/amdmct/mct/mctchi_d.c
View File

@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
#include "mct_d.h"
void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA)

1
src/northbridge/amd/amdmct/mct/mctcsi_d.c
View File

@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include "mct_d.h"
/* Low swap bit vs bank size encoding (physical, not logical address bit)
* ;To calculate the number by hand, add the number of Bank address bits

28
src/northbridge/amd/amdmct/mct/mctdqs_d.c
View File

@ -13,6 +13,9 @@
* GNU General Public License for more details.
*/
#include "mct_d.h"
#include <cpu/x86/cr.h>
#include <cpu/amd/mtrr.h>
static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u16 like,
@ -38,30 +41,20 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat,
u32 addr_lo);
static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat,
u32 addr_lo);
static void SetTargetWTIO_D(u32 TestAddr);
static void ResetTargetWTIO_D(void);
static void ReadDQSTestPattern_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat,
u32 TestAddr_lo);
void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index);
u8 mct_DisableDimmEccEn_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat);
static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat,
u8 ChipSel);
static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat,
u8 cs_start);
u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 Channel,
u8 receiver, u8 *valid);
static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat,
u32 *buffer);
#define DQS_TRAIN_DEBUG 0
static void print_debug_dqs(const char *str, u32 val, u8 level)
void print_debug_dqs(const char *str, u32 val, u8 level)
{
#if DQS_TRAIN_DEBUG > 0
if (DQS_TRAIN_DEBUG >= level) {
@ -70,7 +63,7 @@ static void print_debug_dqs(const char *str, u32 val, u8 level)
#endif
}
static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level)
void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level)
{
#if DQS_TRAIN_DEBUG > 0
if (DQS_TRAIN_DEBUG >= level) {
@ -193,9 +186,6 @@ static const u32 TestPatternJD1b_D[] = {
0x80808080,0x80808080,0x80808080,0x80808080 /* QW7,CHA-B, DQ7-ODD */
};
const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11};
void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA, u8 Pass)
{
@ -653,7 +643,7 @@ static void TrainWriteDQS_D(struct MCTStatStruc *pMCTstat,
}
static void proc_IOCLFLUSH_D(u32 addr_hi)
void proc_IOCLFLUSH_D(u32 addr_hi)
{
SetTargetWTIO_D(addr_hi);
proc_CLFLUSH(addr_hi);
@ -820,7 +810,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat,
}
}
static void SetTargetWTIO_D(u32 TestAddr)
void SetTargetWTIO_D(u32 TestAddr)
{
u32 lo, hi;
hi = TestAddr >> 24;
@ -832,7 +822,7 @@ static void SetTargetWTIO_D(u32 TestAddr)
}
static void ResetTargetWTIO_D(void)
void ResetTargetWTIO_D(void)
{
u32 lo, hi;
@ -1173,7 +1163,7 @@ exitGetAddr:
}
static void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat,
void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat,
u32 TestAddr, u8 pattern)
{

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