75a3d1fb7c
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
44 lines
1.8 KiB
C
44 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef AMDFAM10_RAMINIT_H
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#define AMDFAM10_RAMINIT_H
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#include <device/pci.h>
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#include <northbridge/amd/amdmct/amddefs.h>
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#include <northbridge/amd/amdmct/wrappers/mcti.h>
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struct sys_info;
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struct DCTStatStruc;
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struct MCTStatStruc;
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int mctRead_SPD(u32 smaddr, u32 reg);
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void mctSMBhub_Init(u32 node);
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void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node);
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void raminit_amdmct(struct sys_info *sysinfo);
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void amdmct_cbmem_store_info(struct sys_info *sysinfo);
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void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr);
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uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq);
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u8 mctGetProcessorPackageType(void);
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void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val);
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uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg);
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uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index);
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void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data);
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void fam15h_switch_dct(uint32_t dev, uint8_t dct);
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uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg);
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void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val);
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#endif
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