mb/dell/optiplex_9020: Implement late HWM initialization
There are 4 different chassis types specified by vendor firmware, each with a slightly different HWM configuration. The chassis type to use is determined at runtime by reading a set of 4 PCH GPIOs: 70, 38, 17, and 1. Additionally vendor firmware also provides an option to run the fans at full speed. This is substituted with a coreboot nvram option in this implementation. This was tested to make fan control work on my OptiPlex 7020 SFF. NOTE: This is superficially similar to the OptiPlex 9010's SCH5545 however the OptiPlex 9020's SCH5555 does not use externally programmed EC firmware. Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81529 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mate Kukri
Felix Held
@@ -2,4 +2,5 @@
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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bootblock-y += bootblock.c
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ramstage-y += sch5555_ec.c
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bootblock-y += bootblock.c sch5555_ec.c
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@@ -4,29 +4,14 @@
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#include <device/pnp_ops.h>
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#include <superio/smsc/sch555x/sch555x.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
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{
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// Clear EC-to-Host mailbox
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uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
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outb(tmp, SCH555x_EMI_IOBASE + 1);
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// Send address and value to the EC
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sch555x_emi_write16(0, (addr1 * 2) | 0x101);
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sch555x_emi_write32(4, val | (addr2 << 16));
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// Wait for acknowledgement message from EC
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outb(1, SCH555x_EMI_IOBASE);
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size_t timeout = 0;
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do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
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}
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#include "sch5555_ec.h"
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struct ec_init_entry {
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uint16_t addr;
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uint8_t val;
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};
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static void ec_init(void)
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static void bootblock_ec_init(void)
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{
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/*
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* Tables from CORE_PEI
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@@ -42,7 +27,7 @@ static void ec_init(void)
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};
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for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i)
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ec_write(2, init_table1[i].addr, init_table1[i].val);
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sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val);
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static const struct ec_init_entry init_table2[] = {
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{0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f},
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@@ -60,7 +45,7 @@ static void ec_init(void)
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};
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for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i)
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ec_write(1, init_table2[i].addr, init_table2[i].val);
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sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val);
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/*
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* Table from PeiHwmInit
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@@ -89,7 +74,7 @@ static void ec_init(void)
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};
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for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i)
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ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val);
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sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val);
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}
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#define SCH555x_IOBASE 0x2e
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@@ -108,9 +93,9 @@ void mainboard_config_superio(void)
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outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
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outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
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// Magic EC init
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ec_init();
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// Perform bootblock EC initialization
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bootblock_ec_init();
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// Magic EC init is needed for UART1 initialization to work
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// Bootblock EC initialization is required for UART1 to work
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sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@@ -3,3 +3,4 @@ boot_option=Fallback
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debug_level=Debug
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nmi=Disable
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power_on_after_fail=Disable
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fan_full_speed=Disable
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@@ -21,6 +21,9 @@ entries
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408 1 e 1 nmi
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409 2 e 5 power_on_after_fail
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# coreboot config options: EC
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412 1 e 1 fan_full_speed
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# coreboot config options: check sums
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984 16 h 0 check_sum
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@@ -1,7 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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#include <drivers/intel/gma/int15.h>
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#include <option.h>
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#include <southbridge/intel/common/gpio.h>
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#include "sch5555_ec.h"
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static void mainboard_enable(struct device *dev)
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{
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@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev)
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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#define HWM_TAB_ADD_TEMP_TARGET 1
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#define HWM_TAB_PKG_POWER_ANY 0xffff
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#define CHASSIS_TYPE_UNKNOWN 0xff
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struct hwm_tab_entry {
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uint16_t addr;
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uint8_t val;
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uint8_t flags;
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uint16_t pkg_power;
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};
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struct hwm_tab_entry HWM_TAB3[] = {
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{ 0x005, 0x33, 0, 0xffff },
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{ 0x018, 0x2f, 0, 0xffff },
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{ 0x019, 0x2f, 0, 0xffff },
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{ 0x01a, 0x2f, 0, 0xffff },
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{ 0x080, 0x00, 0, 0xffff },
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{ 0x081, 0x00, 0, 0xffff },
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{ 0x083, 0xbb, 0, 0xffff },
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{ 0x085, 0x8a, 0, 0x0010 },
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{ 0x086, 0x4c, 0, 0x0010 },
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{ 0x08a, 0x66, 0, 0x0010 },
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{ 0x08b, 0x5b, 0, 0x0010 },
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{ 0x090, 0x65, 0, 0xffff },
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{ 0x091, 0x70, 0, 0xffff },
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{ 0x092, 0x86, 0, 0xffff },
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{ 0x096, 0xa4, 0, 0xffff },
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{ 0x097, 0xa4, 0, 0xffff },
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{ 0x098, 0xa4, 0, 0xffff },
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{ 0x09b, 0xa4, 0, 0xffff },
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{ 0x0a0, 0x0e, 0, 0xffff },
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{ 0x0a1, 0x0e, 0, 0xffff },
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{ 0x0ae, 0x7c, 0, 0xffff },
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{ 0x0af, 0x86, 0, 0xffff },
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{ 0x0b0, 0x9a, 0, 0xffff },
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{ 0x0b3, 0x9a, 0, 0xffff },
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{ 0x0b6, 0x08, 0, 0xffff },
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{ 0x0b7, 0x08, 0, 0xffff },
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{ 0x0ea, 0x64, 0, 0x0020 },
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{ 0x0ea, 0x5c, 0, 0x0010 },
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{ 0x0ef, 0xff, 0, 0xffff },
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{ 0x0f8, 0x15, 0, 0xffff },
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{ 0x0f9, 0x00, 0, 0xffff },
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{ 0x0f0, 0x30, 0, 0xffff },
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{ 0x0fd, 0x01, 0, 0xffff },
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{ 0x1a1, 0x00, 0, 0xffff },
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{ 0x1a2, 0x00, 0, 0xffff },
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{ 0x1b1, 0x08, 0, 0xffff },
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{ 0x1be, 0x99, 0, 0xffff },
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{ 0x280, 0xa0, 0, 0x0010 },
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{ 0x281, 0x0f, 0, 0x0010 },
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{ 0x282, 0x03, 0, 0xffff },
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{ 0x283, 0x0a, 0, 0xffff },
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{ 0x284, 0x80, 0, 0xffff },
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{ 0x285, 0x03, 0, 0xffff },
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{ 0x288, 0x68, 0, 0x0010 },
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{ 0x289, 0x10, 0, 0x0010 },
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{ 0x28a, 0x03, 0, 0xffff },
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{ 0x28b, 0x0a, 0, 0xffff },
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{ 0x28c, 0x80, 0, 0xffff },
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{ 0x28d, 0x03, 0, 0xffff },
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};
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struct hwm_tab_entry HWM_TAB4[] = {
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{ 0x005, 0x33, 0, 0xffff },
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{ 0x018, 0x2f, 0, 0xffff },
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{ 0x019, 0x2f, 0, 0xffff },
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{ 0x01a, 0x2f, 0, 0xffff },
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{ 0x080, 0x00, 0, 0xffff },
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{ 0x081, 0x00, 0, 0xffff },
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{ 0x083, 0xbb, 0, 0xffff },
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{ 0x085, 0x99, 0, 0x0020 },
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{ 0x085, 0xad, 0, 0x0010 },
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{ 0x086, 0x1c, 0, 0xffff },
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{ 0x08a, 0x39, 0, 0x0020 },
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{ 0x08a, 0x41, 0, 0x0010 },
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{ 0x08b, 0x76, 0, 0x0020 },
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{ 0x08b, 0x8b, 0, 0x0010 },
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{ 0x090, 0x5e, 0, 0xffff },
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{ 0x091, 0x5e, 0, 0xffff },
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{ 0x092, 0x86, 0, 0xffff },
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{ 0x096, 0xa4, 0, 0xffff },
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{ 0x097, 0xa4, 0, 0xffff },
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{ 0x098, 0xa4, 0, 0xffff },
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{ 0x09b, 0xa4, 0, 0xffff },
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{ 0x0a0, 0x0a, 0, 0xffff },
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{ 0x0a1, 0x0a, 0, 0xffff },
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{ 0x0ae, 0x7c, 0, 0xffff },
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{ 0x0af, 0x7c, 0, 0xffff },
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{ 0x0b0, 0x9a, 0, 0xffff },
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{ 0x0b3, 0x7c, 0, 0xffff },
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{ 0x0b6, 0x08, 0, 0xffff },
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{ 0x0b7, 0x08, 0, 0xffff },
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{ 0x0ea, 0x64, 0, 0x0020 },
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{ 0x0ea, 0x5c, 0, 0x0010 },
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{ 0x0ef, 0xff, 0, 0xffff },
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{ 0x0f8, 0x15, 0, 0xffff },
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{ 0x0f9, 0x00, 0, 0xffff },
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{ 0x0f0, 0x30, 0, 0xffff },
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{ 0x0fd, 0x01, 0, 0xffff },
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{ 0x1a1, 0x00, 0, 0xffff },
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{ 0x1a2, 0x00, 0, 0xffff },
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{ 0x1b1, 0x08, 0, 0xffff },
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{ 0x1be, 0x90, 0, 0xffff },
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{ 0x280, 0x94, 0, 0x0020 },
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{ 0x281, 0x11, 0, 0x0020 },
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{ 0x280, 0x94, 0, 0x0010 },
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{ 0x281, 0x11, 0, 0x0010 },
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{ 0x282, 0x03, 0, 0xffff },
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{ 0x283, 0x0a, 0, 0xffff },
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{ 0x284, 0x80, 0, 0xffff },
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{ 0x285, 0x03, 0, 0xffff },
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{ 0x288, 0x28, 0, 0x0020 },
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{ 0x289, 0x0a, 0, 0x0020 },
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{ 0x288, 0x28, 0, 0x0010 },
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{ 0x289, 0x0a, 0, 0x0010 },
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{ 0x28a, 0x03, 0, 0xffff },
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{ 0x28b, 0x0a, 0, 0xffff },
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{ 0x28c, 0x80, 0, 0xffff },
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{ 0x28d, 0x03, 0, 0xffff },
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};
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struct hwm_tab_entry HWM_TAB5[] = {
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{ 0x005, 0x33, 0, 0xffff },
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{ 0x018, 0x2f, 0, 0xffff },
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{ 0x019, 0x2f, 0, 0xffff },
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{ 0x01a, 0x2f, 0, 0xffff },
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{ 0x080, 0x00, 0, 0xffff },
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{ 0x081, 0x00, 0, 0xffff },
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{ 0x083, 0xbb, 0, 0xffff },
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{ 0x085, 0x66, 0, 0x0020 },
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{ 0x085, 0x5d, 0, 0x0010 },
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{ 0x086, 0x1c, 0, 0xffff },
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{ 0x08a, 0x39, 0, 0x0020 },
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{ 0x08a, 0x41, 0, 0x0010 },
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{ 0x08b, 0x76, 0, 0x0020 },
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{ 0x08b, 0x80, 0, 0x0010 },
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{ 0x090, 0x5d, 0, 0x0020 },
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{ 0x090, 0x5e, 0, 0x0010 },
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{ 0x091, 0x5e, 0, 0xffff },
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{ 0x092, 0x86, 0, 0xffff },
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{ 0x096, 0xa4, 0, 0xffff },
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{ 0x097, 0xa4, 0, 0xffff },
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{ 0x098, 0xa3, 0, 0x0020 },
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{ 0x098, 0xa4, 0, 0x0010 },
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{ 0x09b, 0xa4, 0, 0xffff },
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{ 0x0a0, 0x08, 0, 0xffff },
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{ 0x0a1, 0x0a, 0, 0xffff },
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{ 0x0ae, 0x7c, 0, 0xffff },
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{ 0x0af, 0x7c, 0, 0xffff },
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{ 0x0b0, 0x9a, 0, 0xffff },
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{ 0x0b3, 0x7c, 0, 0xffff },
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{ 0x0b6, 0x08, 0, 0xffff },
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{ 0x0b7, 0x08, 0, 0xffff },
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{ 0x0ea, 0x64, 0, 0x0020 },
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{ 0x0ea, 0x5c, 0, 0x0010 },
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{ 0x0ef, 0xff, 0, 0xffff },
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{ 0x0f8, 0x15, 0, 0xffff },
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{ 0x0f9, 0x00, 0, 0xffff },
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{ 0x0f0, 0x30, 0, 0xffff },
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{ 0x0fd, 0x01, 0, 0xffff },
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{ 0x1a1, 0x00, 0, 0xffff },
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{ 0x1a2, 0x00, 0, 0xffff },
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{ 0x1b1, 0x08, 0, 0xffff },
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{ 0x1be, 0x98, 0, 0x0020 },
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{ 0x1be, 0x90, 0, 0x0010 },
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{ 0x280, 0x94, 0, 0x0020 },
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{ 0x281, 0x11, 0, 0x0020 },
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{ 0x280, 0x94, 0, 0x0010 },
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{ 0x281, 0x11, 0, 0x0010 },
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{ 0x282, 0x03, 0, 0xffff },
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{ 0x283, 0x0a, 0, 0xffff },
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{ 0x284, 0x80, 0, 0xffff },
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{ 0x285, 0x03, 0, 0xffff },
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{ 0x288, 0x28, 0, 0x0020 },
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{ 0x289, 0x0a, 0, 0x0020 },
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{ 0x288, 0x28, 0, 0x0010 },
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{ 0x289, 0x0a, 0, 0x0010 },
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{ 0x28a, 0x03, 0, 0xffff },
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{ 0x28b, 0x0a, 0, 0xffff },
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{ 0x28c, 0x80, 0, 0xffff },
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{ 0x28d, 0x03, 0, 0xffff },
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};
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struct hwm_tab_entry HWM_TAB6[] = {
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{ 0x005, 0x33, 0, 0xffff },
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{ 0x018, 0x2f, 0, 0xffff },
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{ 0x019, 0x2f, 0, 0xffff },
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{ 0x01a, 0x2f, 0, 0xffff },
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{ 0x080, 0x00, 0, 0xffff },
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{ 0x081, 0x00, 0, 0xffff },
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{ 0x083, 0xbb, 0, 0xffff },
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{ 0x085, 0x98, 0, 0xffff },
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{ 0x086, 0x3c, 0, 0xffff },
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{ 0x08a, 0x39, 0, 0x0020 },
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{ 0x08a, 0x3d, 0, 0x0010 },
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{ 0x08b, 0x44, 0, 0x0020 },
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{ 0x08b, 0x51, 0, 0x0010 },
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{ 0x090, 0x61, 0, 0xffff },
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{ 0x091, 0x6d, 0, 0xffff },
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{ 0x092, 0x86, 0, 0xffff },
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{ 0x096, 0xa4, 0, 0xffff },
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{ 0x097, 0xa4, 0, 0xffff },
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{ 0x098, 0x9f, 0, 0x0020 },
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{ 0x098, 0xa4, 0, 0x0010 },
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{ 0x09b, 0xa4, 0, 0xffff },
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{ 0x0a0, 0x0e, 0, 0xffff },
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{ 0x0a1, 0x0e, 0, 0xffff },
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{ 0x0ae, 0x7c, 0, 0xffff },
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{ 0x0af, 0x7c, 0, 0xffff },
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{ 0x0b0, 0x9b, 0, 0x0020 },
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{ 0x0b0, 0x98, 0, 0x0010 },
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{ 0x0b3, 0x9a, 0, 0xffff },
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{ 0x0b6, 0x08, 0, 0xffff },
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{ 0x0b7, 0x08, 0, 0xffff },
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{ 0x0ea, 0x64, 0, 0x0020 },
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{ 0x0ea, 0x5c, 0, 0x0010 },
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{ 0x0ef, 0xff, 0, 0xffff },
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{ 0x0f8, 0x15, 0, 0xffff },
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{ 0x0f9, 0x00, 0, 0xffff },
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{ 0x0f0, 0x30, 0, 0xffff },
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{ 0x0fd, 0x01, 0, 0xffff },
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{ 0x1a1, 0x00, 0, 0xffff },
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{ 0x1a2, 0x00, 0, 0xffff },
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{ 0x1b1, 0x08, 0, 0xffff },
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{ 0x1be, 0x9a, 0, 0x0020 },
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{ 0x1be, 0x96, 0, 0x0010 },
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{ 0x280, 0x94, 0, 0x0020 },
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{ 0x281, 0x11, 0, 0x0020 },
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{ 0x280, 0x94, 0, 0x0010 },
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{ 0x281, 0x11, 0, 0x0010 },
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{ 0x282, 0x03, 0, 0xffff },
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{ 0x283, 0x0a, 0, 0xffff },
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{ 0x284, 0x80, 0, 0xffff },
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{ 0x285, 0x03, 0, 0xffff },
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{ 0x288, 0x94, 0, 0x0020 },
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{ 0x289, 0x11, 0, 0x0020 },
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{ 0x288, 0x94, 0, 0x0010 },
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{ 0x289, 0x11, 0, 0x0010 },
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{ 0x28a, 0x03, 0, 0xffff },
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{ 0x28b, 0x0a, 0, 0xffff },
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{ 0x28c, 0x80, 0, 0xffff },
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{ 0x28d, 0x03, 0, 0xffff },
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};
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|
||||
static uint8_t get_chassis_type(void)
|
||||
{
|
||||
uint8_t gpio_chassis_type;
|
||||
|
||||
// Read chassis type from GPIO
|
||||
gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
|
||||
get_gpio(17) << 1 | get_gpio(1);
|
||||
|
||||
printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
|
||||
|
||||
// Turn it into internal chassis index
|
||||
switch (gpio_chassis_type) {
|
||||
case 0x08:
|
||||
case 0x0a:
|
||||
return 4;
|
||||
case 0x0b:
|
||||
return 3;
|
||||
case 0x0c:
|
||||
return 5;
|
||||
case 0x0d: // SFF
|
||||
case 0x0e:
|
||||
case 0x0f:
|
||||
return 6;
|
||||
default:
|
||||
return CHASSIS_TYPE_UNKNOWN;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static uint8_t get_temp_target(void)
|
||||
{
|
||||
uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff;
|
||||
if (!val)
|
||||
val = 20;
|
||||
return 0x95 - val;
|
||||
}
|
||||
|
||||
static uint16_t get_pkg_power(void)
|
||||
{
|
||||
uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf;
|
||||
if (rapl_power_unit)
|
||||
rapl_power_unit = 2 << (rapl_power_unit - 1);
|
||||
uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff;
|
||||
if (pkg_power_info / rapl_power_unit > 0x41)
|
||||
return 32;
|
||||
else
|
||||
return 16;
|
||||
}
|
||||
|
||||
static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size)
|
||||
{
|
||||
uint8_t temp_target = get_temp_target();
|
||||
uint16_t pkg_power = get_pkg_power();
|
||||
|
||||
printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target);
|
||||
printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power);
|
||||
|
||||
for (size_t i = 0; i < size; ++i) {
|
||||
// Skip entry if it doesn't apply for this package power
|
||||
if (arr[i].pkg_power != pkg_power &&
|
||||
arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY)
|
||||
continue;
|
||||
|
||||
uint8_t val = arr[i].val;
|
||||
|
||||
// Add temp target to value if requested (current tables never do)
|
||||
if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET)
|
||||
val += temp_target;
|
||||
|
||||
// Perform write
|
||||
sch5555_mbox_write(1, arr[i].addr, val);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void sch5555_ec_hwm_init(void *arg)
|
||||
{
|
||||
uint8_t chassis_type, saved_2fc;
|
||||
|
||||
printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n");
|
||||
|
||||
saved_2fc = sch5555_mbox_read(1, 0x2fc);
|
||||
sch5555_mbox_write(1, 0x2fc, 0xa0);
|
||||
sch5555_mbox_write(1, 0x2fd, 0x32);
|
||||
|
||||
chassis_type = get_chassis_type();
|
||||
|
||||
if (chassis_type != CHASSIS_TYPE_UNKNOWN) {
|
||||
printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n");
|
||||
}
|
||||
|
||||
// Apply HWM table based on chassis type
|
||||
switch (chassis_type) {
|
||||
case 3:
|
||||
apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3));
|
||||
break;
|
||||
case 4:
|
||||
apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4));
|
||||
break;
|
||||
case 5:
|
||||
apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5));
|
||||
break;
|
||||
case 6:
|
||||
apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6));
|
||||
break;
|
||||
}
|
||||
|
||||
// NOTE: vendor firmware applies these when "max core address" > 2
|
||||
// i think this is always the case
|
||||
sch5555_mbox_write(1, 0x9e, 0x30);
|
||||
sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea));
|
||||
|
||||
sch5555_mbox_write(1, 0x2fc, saved_2fc);
|
||||
|
||||
// Apply full speed fan config if requested or if the chassis type is unknown
|
||||
if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) {
|
||||
printk(BIOS_DEBUG, "Setting full fan speed\n");
|
||||
sch5555_mbox_write(1, 0x80, 0x60 | sch5555_mbox_read(1, 0x80));
|
||||
sch5555_mbox_write(1, 0x81, 0x60 | sch5555_mbox_read(1, 0x81));
|
||||
}
|
||||
|
||||
sch5555_mbox_read(1, 0xb8);
|
||||
|
||||
if ((chassis_type == 4 || chassis_type == 5) && sch5555_mbox_read(1, 0x26) == 0) {
|
||||
sch5555_mbox_write(1, 0xa0, sch5555_mbox_read(1, 0xa0) & 0xfb);
|
||||
sch5555_mbox_write(1, 0xa1, sch5555_mbox_read(1, 0xa1) & 0xfb);
|
||||
sch5555_mbox_write(1, 0xa2, sch5555_mbox_read(1, 0xa2) & 0xfb);
|
||||
sch5555_mbox_write(1, 0x8a, 0x99);
|
||||
sch5555_mbox_write(1, 0x8b, 0x47);
|
||||
sch5555_mbox_write(1, 0x8c, 0x91);
|
||||
}
|
||||
}
|
||||
|
||||
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL);
|
||||
|
||||
54
src/mainboard/dell/optiplex_9020/sch5555_ec.c
Normal file
54
src/mainboard/dell/optiplex_9020/sch5555_ec.c
Normal file
@@ -0,0 +1,54 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_ops.h>
|
||||
#include <superio/smsc/sch555x/sch555x.h>
|
||||
#include "sch5555_ec.h"
|
||||
|
||||
uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2)
|
||||
{
|
||||
// clear ec-to-host mailbox
|
||||
uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
|
||||
outb(tmp, SCH555x_EMI_IOBASE + 1);
|
||||
|
||||
// send address
|
||||
outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
|
||||
outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4);
|
||||
|
||||
outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
|
||||
outl(addr2 << 16, SCH555x_EMI_IOBASE + 4);
|
||||
|
||||
// send message to ec
|
||||
outb(1, SCH555x_EMI_IOBASE);
|
||||
|
||||
// wait for ack
|
||||
for (size_t retry = 0; retry < 0xfff; ++retry)
|
||||
if (inb(SCH555x_EMI_IOBASE + 1) & 1)
|
||||
break;
|
||||
|
||||
// read result
|
||||
outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2);
|
||||
return inb(SCH555x_EMI_IOBASE + 4);
|
||||
}
|
||||
|
||||
void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val)
|
||||
{
|
||||
// clear ec-to-host mailbox
|
||||
uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
|
||||
outb(tmp, SCH555x_EMI_IOBASE + 1);
|
||||
|
||||
// send address and value
|
||||
outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
|
||||
outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4);
|
||||
|
||||
outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
|
||||
outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4);
|
||||
|
||||
// send message to ec
|
||||
outb(1, SCH555x_EMI_IOBASE);
|
||||
|
||||
// wait for ack
|
||||
for (size_t retry = 0; retry < 0xfff; ++retry)
|
||||
if (inb(SCH555x_EMI_IOBASE + 1) & 1)
|
||||
break;
|
||||
}
|
||||
10
src/mainboard/dell/optiplex_9020/sch5555_ec.h
Normal file
10
src/mainboard/dell/optiplex_9020/sch5555_ec.h
Normal file
@@ -0,0 +1,10 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __SCH5555_EC_H__
|
||||
#define __SCH5555_EC_H__
|
||||
|
||||
uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2);
|
||||
|
||||
void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user