sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT

Backport commit cf544ac (broadwell: Remove XHCI workarounds on WPT).
Newer Lynxpoint reference code shows LPT-H also uses these workarounds.

Also, add the `ISWP` object (Name or Method) to test for WildcatPoint.

Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46960
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

src/southbridge/intel/lynxpoint/acpi/pch.asl

@@ -19,6 +19,25 @@ Scope (\)
 		, 5,
 		HPTE, 1,	// Address Enable
 	}
+
+	/*
+	 * Check PCH type
+	 * Return 1 if PCH is WildcatPoint
+	 * Return 0 if PCH is LynxPoint
+	 */
+#if CONFIG(INTEL_LYNXPOINT_LP)
+	Method (ISWP)
+	{
+		Local0 = \_SB.PCI0.LPCB.PDID & 0xfff0
+		If (Local0 == 0x9cc0) {
+			Return (1)
+		} Else {
+			Return (0)
+		}
+	}
+#else
+	Name (ISWP, 0)
+#endif
 }
 
 // High Definition Audio (Azalia) 0:1b.0

src/southbridge/intel/lynxpoint/acpi/xhci.asl

@@ -221,25 +221,39 @@ Device (XHCI)
 		}
 
 #if CONFIG(INTEL_LYNXPOINT_LP)
-		// Clear PCI 0xB0[14:13]
-		^MB13 = 0
-		^MB14 = 0
+		If (!\ISWP()) {
+			// Clear PCI 0xB0[14:13]
+			^MB13 = 0
+			^MB14 = 0
 
-		// Clear MMIO 0x816C[14,2]
-		CLK0 = 0
-		CLK1 = 0
+			// Clear MMIO 0x816C[14,2]
+			CLK0 = 0
+			CLK1 = 0
 
-		// Set MMIO 0x8154[31]
-		CLK2 = 1
+			// Set MMIO 0x8154[31]
+			CLK2 = 1
 
-		// Handle per-port reset if needed
-		LPS0 ()
+			// Handle per-port reset if needed
+			LPS0 ()
 
-		// Set MMIO 0x80e0[15]
-		AX15 = 1
+			// Set MMIO 0x80e0[15]
+			AX15 = 1
+
+			// Clear PCI CFG offset 0x40[11]
+			^SWAI = 0
+
+			// Clear PCI CFG offset 0x44[13:12]
+			^SAIP = 0
+		}
 #else
 		// Set MMIO 0x8154[31]
 		CLK2 = 1
+
+		// Clear PCI CFG offset 0x40[11]
+		^SWAI = 0
+
+		// Clear PCI CFG offset 0x44[13:12]
+		^SAIP = 0
 #endif
 
 		// Clear PCI CFG offset 0x40[11]
@@ -286,22 +300,36 @@ Device (XHCI)
 		}
 
 #if CONFIG(INTEL_LYNXPOINT_LP)
-		// Set PCI 0xB0[14:13]
-		^MB13 = 1
-		^MB14 = 1
+		If (!\ISWP()) {
+			// Set PCI 0xB0[14:13]
+			^MB13 = 1
+			^MB14 = 1
 
-		// Set MMIO 0x816C[14,2]
-		CLK0 = 1
-		CLK1 = 1
+			// Set MMIO 0x816C[14,2]
+			CLK0 = 1
+			CLK1 = 1
 
-		// Clear MMIO 0x8154[31]
-		CLK2 = 0
+			// Clear MMIO 0x8154[31]
+			CLK2 = 0
 
-		// Clear MMIO 0x80e0[15]
-		AX15 = 0
+			// Clear MMIO 0x80e0[15]
+			AX15 = 0
+
+			// Set PCI CFG offset 0x40[11]
+			^SWAI = 1
+
+			// Set PCI CFG offset 0x44[13:12]
+			^SAIP = 1
+		}
 #else
 		// Clear MMIO 0x8154[31]
 		CLK2 = 0
+
+		// Set PCI CFG offset 0x40[11]
+		^SWAI = 1
+
+		// Set PCI CFG offset 0x44[13:12]
+		^SAIP = 1
 #endif
 
 		// Set PCI CFG offset 0x40[11]