sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT
Backport commit cf544ac
(broadwell: Remove XHCI workarounds on WPT).
Newer Lynxpoint reference code shows LPT-H also uses these workarounds.
Also, add the `ISWP` object (Name or Method) to test for WildcatPoint.
Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46960
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
committed by
Matt DeVillier
parent
e49d03395f
commit
76653f638f
@@ -19,6 +19,25 @@ Scope (\)
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, 5,
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HPTE, 1, // Address Enable
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}
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/*
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* Check PCH type
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* Return 1 if PCH is WildcatPoint
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* Return 0 if PCH is LynxPoint
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*/
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#if CONFIG(INTEL_LYNXPOINT_LP)
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Method (ISWP)
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{
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Local0 = \_SB.PCI0.LPCB.PDID & 0xfff0
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If (Local0 == 0x9cc0) {
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Return (1)
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} Else {
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Return (0)
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}
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}
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#else
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Name (ISWP, 0)
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#endif
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}
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// High Definition Audio (Azalia) 0:1b.0
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@@ -221,25 +221,39 @@ Device (XHCI)
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}
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#if CONFIG(INTEL_LYNXPOINT_LP)
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// Clear PCI 0xB0[14:13]
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^MB13 = 0
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^MB14 = 0
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If (!\ISWP()) {
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// Clear PCI 0xB0[14:13]
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^MB13 = 0
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^MB14 = 0
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// Clear MMIO 0x816C[14,2]
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CLK0 = 0
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CLK1 = 0
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// Clear MMIO 0x816C[14,2]
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CLK0 = 0
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CLK1 = 0
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// Set MMIO 0x8154[31]
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CLK2 = 1
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// Set MMIO 0x8154[31]
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CLK2 = 1
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// Handle per-port reset if needed
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LPS0 ()
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// Handle per-port reset if needed
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LPS0 ()
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// Set MMIO 0x80e0[15]
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AX15 = 1
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// Set MMIO 0x80e0[15]
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AX15 = 1
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// Clear PCI CFG offset 0x40[11]
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^SWAI = 0
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// Clear PCI CFG offset 0x44[13:12]
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^SAIP = 0
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}
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#else
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// Set MMIO 0x8154[31]
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CLK2 = 1
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// Clear PCI CFG offset 0x40[11]
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^SWAI = 0
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// Clear PCI CFG offset 0x44[13:12]
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^SAIP = 0
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#endif
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// Clear PCI CFG offset 0x40[11]
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@@ -286,22 +300,36 @@ Device (XHCI)
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}
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#if CONFIG(INTEL_LYNXPOINT_LP)
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// Set PCI 0xB0[14:13]
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^MB13 = 1
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^MB14 = 1
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If (!\ISWP()) {
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// Set PCI 0xB0[14:13]
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^MB13 = 1
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^MB14 = 1
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// Set MMIO 0x816C[14,2]
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CLK0 = 1
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CLK1 = 1
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// Set MMIO 0x816C[14,2]
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CLK0 = 1
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CLK1 = 1
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// Clear MMIO 0x8154[31]
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CLK2 = 0
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// Clear MMIO 0x8154[31]
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CLK2 = 0
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// Clear MMIO 0x80e0[15]
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AX15 = 0
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// Clear MMIO 0x80e0[15]
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AX15 = 0
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// Set PCI CFG offset 0x40[11]
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^SWAI = 1
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// Set PCI CFG offset 0x44[13:12]
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^SAIP = 1
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}
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#else
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// Clear MMIO 0x8154[31]
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CLK2 = 0
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// Set PCI CFG offset 0x40[11]
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^SWAI = 1
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// Set PCI CFG offset 0x44[13:12]
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^SAIP = 1
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#endif
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// Set PCI CFG offset 0x40[11]
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