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sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT

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Backport commit cf544ac (broadwell: Remove XHCI workarounds on WPT).
Newer Lynxpoint reference code shows LPT-H also uses these workarounds.

Also, add the `ISWP` object (Name or Method) to test for WildcatPoint.

Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46960
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Angel Pons
2020-10-29 13:31:08 +01:00
committed by Matt DeVillier
parent e49d03395f
commit 76653f638f
2 changed files with 69 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/southbridge/intel/lynxpoint/acpi/pch.asl
View File

@@ -19,6 +19,25 @@ Scope (\)
, 5, , 5,
HPTE, 1, // Address Enable HPTE, 1, // Address Enable
} }
/*
* Check PCH type
* Return 1 if PCH is WildcatPoint
* Return 0 if PCH is LynxPoint
*/
#if CONFIG(INTEL_LYNXPOINT_LP)
Method (ISWP)
{
Local0 = \_SB.PCI0.LPCB.PDID & 0xfff0
If (Local0 == 0x9cc0) {
Return (1)
} Else {
Return (0)
}
}
#else
Name (ISWP, 0)
#endif
} }
// High Definition Audio (Azalia) 0:1b.0 // High Definition Audio (Azalia) 0:1b.0

72
src/southbridge/intel/lynxpoint/acpi/xhci.asl
View File

@@ -221,25 +221,39 @@ Device (XHCI)
} }
#if CONFIG(INTEL_LYNXPOINT_LP) #if CONFIG(INTEL_LYNXPOINT_LP)
// Clear PCI 0xB0[14:13] If (!\ISWP()) {
^MB13 = 0 // Clear PCI 0xB0[14:13]
^MB14 = 0 ^MB13 = 0
^MB14 = 0
// Clear MMIO 0x816C[14,2] // Clear MMIO 0x816C[14,2]
CLK0 = 0 CLK0 = 0
CLK1 = 0 CLK1 = 0
// Set MMIO 0x8154[31] // Set MMIO 0x8154[31]
CLK2 = 1 CLK2 = 1
// Handle per-port reset if needed // Handle per-port reset if needed
LPS0 () LPS0 ()
// Set MMIO 0x80e0[15] // Set MMIO 0x80e0[15]
AX15 = 1 AX15 = 1
// Clear PCI CFG offset 0x40[11]
^SWAI = 0
// Clear PCI CFG offset 0x44[13:12]
^SAIP = 0
}
#else #else
// Set MMIO 0x8154[31] // Set MMIO 0x8154[31]
CLK2 = 1 CLK2 = 1
// Clear PCI CFG offset 0x40[11]
^SWAI = 0
// Clear PCI CFG offset 0x44[13:12]
^SAIP = 0
#endif #endif
// Clear PCI CFG offset 0x40[11] // Clear PCI CFG offset 0x40[11]
@@ -286,22 +300,36 @@ Device (XHCI)
} }
#if CONFIG(INTEL_LYNXPOINT_LP) #if CONFIG(INTEL_LYNXPOINT_LP)
// Set PCI 0xB0[14:13] If (!\ISWP()) {
^MB13 = 1 // Set PCI 0xB0[14:13]
^MB14 = 1 ^MB13 = 1
^MB14 = 1
// Set MMIO 0x816C[14,2] // Set MMIO 0x816C[14,2]
CLK0 = 1 CLK0 = 1
CLK1 = 1 CLK1 = 1
// Clear MMIO 0x8154[31] // Clear MMIO 0x8154[31]
CLK2 = 0 CLK2 = 0
// Clear MMIO 0x80e0[15] // Clear MMIO 0x80e0[15]
AX15 = 0 AX15 = 0
// Set PCI CFG offset 0x40[11]
^SWAI = 1
// Set PCI CFG offset 0x44[13:12]
^SAIP = 1
}
#else #else
// Clear MMIO 0x8154[31] // Clear MMIO 0x8154[31]
CLK2 = 0 CLK2 = 0
// Set PCI CFG offset 0x40[11]
^SWAI = 1
// Set PCI CFG offset 0x44[13:12]
^SAIP = 1
#endif #endif
// Set PCI CFG offset 0x40[11] // Set PCI CFG offset 0x40[11]