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soc/intel/mtl: Improve functions in soc_info.c

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Remove debug message since it's static information.
Remove additional uint_8 varience and return below settings
directly:
1. CONFIG_SOC_INTEL_USB2_DEV_MAX
2. CONFIG_SOC_INTEL_USB3_DEV_MAX
3. MAX_TYPE_C_PORTS
4. CONFIG_MAX_TBT_ROOT_PORTS
5. CONFIG_MAX_ROOT_PORTS
6. CONFIG_MAX_PCIE_CLOCK_SRC
7. CONFIG_SOC_INTEL_UART_DEV_MAX
8. CONFIG_SOC_INTEL_I2C_DEV_MAX
9. CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX

BUG=none
TEST=Build and test on rex/karis, system can boot to OS

Change-Id: I26e882d2d9dcbef84718924aaab3864d89c58f39
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Tyler Wang
2024-03-08 10:39:57 +08:00
committed by Felix Held
parent 7ee7b137a7
commit 785a7aab14
1 changed files with 9 additions and 27 deletions
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36
src/soc/intel/meteorlake/soc_info.c
View File

@@ -9,63 +9,45 @@
uint8_t get_max_usb20_port(void)
{
uint8_t usb20_port = CONFIG_SOC_INTEL_USB2_DEV_MAX;
printk(BIOS_DEBUG, "soc_info: max_usb20_port:%d\n", usb20_port);
return usb20_port;
return CONFIG_SOC_INTEL_USB2_DEV_MAX;
}
uint8_t get_max_usb30_port(void)
{
uint8_t usb30_port = CONFIG_SOC_INTEL_USB3_DEV_MAX;
printk(BIOS_DEBUG, "soc_info: max_usb30_port:%d\n", usb30_port);
return usb30_port;
return CONFIG_SOC_INTEL_USB3_DEV_MAX;
}
uint8_t get_max_tcss_port(void)
{
uint8_t tcss_port = MAX_TYPE_C_PORTS;
printk(BIOS_DEBUG, "soc_info: tcss_port:%d\n", tcss_port);
return tcss_port;
return MAX_TYPE_C_PORTS;
}
uint8_t get_max_tbt_pcie_port(void)
{
uint8_t tbt_pcie_port = CONFIG_MAX_TBT_ROOT_PORTS;
printk(BIOS_DEBUG, "soc_info: max_tbt_pcie_port:%d\n", tbt_pcie_port);
return tbt_pcie_port;
return CONFIG_MAX_TBT_ROOT_PORTS;
}
uint8_t get_max_pcie_port(void)
{
uint8_t pcie_port = CONFIG_MAX_ROOT_PORTS;
printk(BIOS_DEBUG, "soc_info: max_pcie_port:%d\n", pcie_port);
return pcie_port;
return CONFIG_MAX_ROOT_PORTS;
}
uint8_t get_max_pcie_clock(void)
{
uint8_t pcie_clock = CONFIG_MAX_PCIE_CLOCK_SRC;
printk(BIOS_DEBUG, "soc_info: max_pcie_clock:%d\n", pcie_clock);
return pcie_clock;
return CONFIG_MAX_PCIE_CLOCK_SRC;
}
uint8_t get_max_uart_port(void)
{
uint8_t uart_port = CONFIG_SOC_INTEL_UART_DEV_MAX;
printk(BIOS_DEBUG, "soc_info: max_uart_port:%d\n", uart_port);
return uart_port;
return CONFIG_SOC_INTEL_UART_DEV_MAX;
}
uint8_t get_max_i2c_port(void)
{
uint8_t i2c_port = CONFIG_SOC_INTEL_I2C_DEV_MAX;
printk(BIOS_DEBUG, "soc_info: max_i2c_port:%d\n", i2c_port);
return i2c_port;
return CONFIG_SOC_INTEL_I2C_DEV_MAX;
}
uint8_t get_max_gspi_port(void)
{
uint8_t gspi_port = CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX;
printk(BIOS_DEBUG, "soc_info: max_gspi_port:%d\n", gspi_port);
return gspi_port;
return CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX;
}