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device/dram/ddr{3,4}: Rename spd_raw_data for specific DDR

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Rename different spd_raw_data[] for DDR3 and DDR4.
This is to solve the conflict when we include both "ddr3.h" and ddr4.h"
for example here: src/device/dram/spd.c.
Otherwise, it won't compile as DDR3 and DDR4 have different
spd_raw_data[] size.

Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes Haouas
2024-05-06 05:11:28 +02:00
parent 0f3316bc71
commit 78ba7a7865
7 changed files with 19 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/device/dram/ddr3.c
View File

@ -97,7 +97,7 @@ u16 spd_ddr3_calc_unique_crc(u8 *spd, int len)
* SPD_STATUS_INVALID_FIELD -- A field with an invalid value was
* detected.
*/
int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd)
int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd)
{
int ret;
u16 crc, spd_crc;
@ -122,7 +122,7 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd)
dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3;
dimm->dimm_type = spd[3] & 0xf;
crc = spd_ddr3_calc_crc(spd, sizeof(spd_raw_data));
crc = spd_ddr3_calc_crc(spd, sizeof(spd_ddr3_raw_data));
/* Compare with the CRC in the SPD */
spd_crc = (spd[127] << 8) + spd[126];
/* Verify the CRC is correct */
@ -390,7 +390,7 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd)
* SPD_STATUS_INVALID_FIELD -- A field with an invalid value was
* detected.
*/
int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd,
int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd,
enum ddr3_xmp_profile profile)
{
int ret;

4
src/device/dram/ddr4.c
View File

@ -70,7 +70,7 @@ const spd_block spd_blocks[] = {
{.type = BLOCK_3, 384, 128, 0}
};
static bool verify_block(const spd_block *block, spd_raw_data spd)
static bool verify_block(const spd_block *block, spd_ddr4_raw_data spd)
{
uint16_t crc, spd_crc;
@ -136,7 +136,7 @@ uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz)
* SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD
* SPD_STATUS_CRC_ERROR -- checksum mismatch
*/
int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd)
int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd)
{
u8 reg8;
u8 bus_width, sdram_width;

6
src/include/device/dram/ddr3.h
View File

@ -153,15 +153,15 @@ enum ddr3_xmp_profile {
DDR3_XMP_PROFILE_2 = 1,
};
typedef u8 spd_raw_data[256];
typedef u8 spd_ddr3_raw_data[SPD_SIZE_MAX_DDR3];
u16 spd_ddr3_calc_crc(u8 *spd, int len);
u16 spd_ddr3_calc_unique_crc(u8 *spd, int len);
int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data);
int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd_data);
int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type);
void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm);
int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm,
spd_raw_data spd,
spd_ddr3_raw_data spd,
enum ddr3_xmp_profile profile);
enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
const u16 selected_freq,

4
src/include/device/dram/ddr4.h
View File

@ -64,9 +64,9 @@ struct dimm_attr_ddr4_st {
bool ecc_extension;
};
typedef u8 spd_raw_data[512];
typedef u8 spd_ddr4_raw_data[SPD_SIZE_MAX_DDR4];
int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd);
int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd);
enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot,
const u16 selected_freq,

2
src/northbridge/intel/haswell/native_raminit/raminit_native.h
View File

@ -33,7 +33,7 @@ enum generic_stepping {
};
struct raminit_dimm_info {
spd_raw_data raw_spd;
spd_ddr3_raw_data raw_spd;
struct dimm_attr_ddr3_st data;
uint8_t spd_addr;
bool valid;

14
src/northbridge/intel/sandybridge/raminit.c
View File

@ -123,7 +123,7 @@ static void setup_sdram_meminfo(ramctr_timing *ctrl)
}
/* Return CRC16 match for all SPDs */
static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
static int verify_crc16_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl)
{
int channel, slot, spd_slot;
int match = 1;
@ -132,13 +132,13 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
for (slot = 0; slot < NUM_SLOTS; slot++) {
spd_slot = 2 * channel + slot;
match &= ctrl->spd_crc[channel][slot] ==
spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data));
}
}
return match;
}
static void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only)
{
int j;
if (id_only) {
@ -150,7 +150,7 @@ static void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
}
}
static void mainboard_get_spd(spd_raw_data *spd, bool id_only)
static void mainboard_get_spd(spd_ddr3_raw_data *spd, bool id_only)
{
const struct northbridge_intel_sandybridge_config *cfg = config_of_soc();
unsigned int i;
@ -192,7 +192,7 @@ static void mainboard_get_spd(spd_raw_data *spd, bool id_only)
} /* CONFIG(HAVE_SPD_IN_CBFS) */
}
static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
static void dram_find_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl)
{
int dimms = 0, ch_dimms;
int channel, slot, spd_slot;
@ -254,7 +254,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
/* Fill in CRC16 for MRC cache */
ctrl->spd_crc[channel][slot] =
spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data));
if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
/* Mark DIMM as invalid */
@ -339,7 +339,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
{
int me_uma_size, cbmem_was_inited, fast_boot, err;
ramctr_timing ctrl;
spd_raw_data spds[4];
spd_ddr3_raw_data spds[4];
size_t mrc_size;
ramctr_timing *ctrl_cached = NULL;

2
src/soc/intel/baytrail/romstage/raminit.c
View File

@ -59,7 +59,7 @@ static void populate_smbios_tables(void *dram_data, int speed, int num_channels)
enum spd_status status;
/* Decode into dimm_attr struct */
status = spd_decode_ddr3(&dimm, *(spd_raw_data *)dram_data);
status = spd_decode_ddr3(&dimm, *(spd_ddr3_raw_data *)dram_data);
/* Some SPDs have bad CRCs, nothing we can do about it */
if (status == SPD_STATUS_OK || status == SPD_STATUS_CRC_ERROR) {